Re: [Qemu-arm] [PATCH] hw/intc/armv7m: Support byte and halfword accesses to CFSR

[Peter Maydell]

On 15 January 2018 at 02:34, Philippe Mathieu-Daudé <address@hidden> wrote:
> Hi Peter,
>
> On 12/08/2017 11:12 AM, Peter Maydell wrote:
>> The Configurable Fault Status Register for ARMv7M and v8M is
>> supposed to be byte and halfword accessible, but we were only
>
> "aligned halfword"

"halfword" is the phrasing the v8M Arm ARM uses. If unaligned
is meant it's always explicitly stated.

>> implementing word accesses. Add support for the other access
>> sizes, which are used by the Zephyr RTOS.

> we have:
>
> static const MemoryRegionOps nvic_sysreg_ops = {
>     .read_with_attrs = nvic_sysreg_read,
>     .write_with_attrs = nvic_sysreg_write,
>     .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> with:
>     /* If true, unaligned accesses are supported.  Otherwise unaligned
>      * accesses throw machine checks.
>      */
>     bool unaligned;
>
> So unaligned halfword should throw excp.
>
> We could add an explicit ".unaligned = false,"

That is the default, and assumed by practically every
MemoryRegionOps struct in QEMU...

thanks
-- PMM