Re: [Qemu-arm] [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]               patchew/address@hidden -> patchew/address@hidden
 * [new tag]               patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
828fdf8039 arm/translate-a64: add all single op FP16 to handle_fp_1src_half
bb12347df0 arm/translate-a64: implement simd_scalar_three_reg_same_fp16
9d90e658c5 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
18e4d6f1d2 arm/translate-a64: add FP16 FMOV to simd_mod_imm
487d21785a arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
e687eee03d arm/helper.c: re-factor rsqrte and add rsqrte_f16
4078596895 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
14e2473a01 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
0080b9feb1 arm/translate-a64: add FP16 FRECPE
322031a5c9 arm/helper.c: re-factor recpe and add recepe_f16
99396effce arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
fc0f9dbd0a arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
ed77588f3f arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
28b6a6a772 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
c8ce2f736d arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
900561ae36 arm/translate-a64: initial decode for simd_two_reg_misc_fp16
d55f8fd2d4 arm/translate-a64: add FP16 x2 ops for simd_indexed
79200bf33e arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
eebcc3aeb6 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
a7d42c109d arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
f4f8f0083b arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
f9994103ca arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to 
simd_three_reg_same_fp16
740b571cc7 arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to 
simd_three_reg_same_fp16
221024b870 arm/translate-a64: initial decode for simd_three_reg_same_fp16
e55cd68b2e arm/translate-a64: handle_3same_64 comment fix
e961c2bee4 arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
c177c95091 target/arm/helper: pass explicit fpst to set_rmode
71fe7953f2 target/arm/cpu.h: add additional float_status flags
c2bbffe04d target/arm/cpu.h: update comment for half-precision values
f5f0e3fa79 target/arm/cpu64: allow fp16 to be disabled
ab954b06bc target/arm/cpu64: introduce ARM_V8_FP16 feature bit
7c3b41efe8 include/exec/helper-head.h: support f16 in helper calls

=== OUTPUT BEGIN ===
Checking PATCH 1/32: include/exec/helper-head.h: support f16 in helper calls...
Checking PATCH 2/32: target/arm/cpu64: introduce ARM_V8_FP16 feature bit...
Checking PATCH 3/32: target/arm/cpu64: allow fp16 to be disabled...
Checking PATCH 4/32: target/arm/cpu.h: update comment for half-precision 
values...
Checking PATCH 5/32: target/arm/cpu.h: add additional float_status flags...
Checking PATCH 6/32: target/arm/helper: pass explicit fpst to set_rmode...
Checking PATCH 7/32: arm/translate-a64: implement half-precision 
F(MIN|MAX)(V|NMV)...
Checking PATCH 8/32: arm/translate-a64: handle_3same_64 comment fix...
Checking PATCH 9/32: arm/translate-a64: initial decode for 
simd_three_reg_same_fp16...
Checking PATCH 10/32: arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to 
simd_three_reg_same_fp16...
Checking PATCH 11/32: arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to 
simd_three_reg_same_fp16...
Checking PATCH 12/32: arm/translate-a64: add FP16 FMULA/X/S to 
simd_three_reg_same_fp16...
Checking PATCH 13/32: arm/translate-a64: add FP16 FR[ECP/SQRT]S to 
simd_three_reg_same_fp16...
Checking PATCH 14/32: arm/translate-a64: add FP16 pairwise ops 
simd_three_reg_same_fp16...
Checking PATCH 15/32: arm/translate-a64: add FP16 FMULX/MLS/FMLA to 
simd_indexed...
WARNING: line over 80 characters
#24: FILE: target/arm/translate-a64.c:10807:
+        if (size == 1 || (size < 2 && !arm_dc_feature(s, 
ARM_FEATURE_V8_FP16))) {

WARNING: line over 80 characters
#74: FILE: target/arm/translate-a64.c:10969:
+                read_vec_element_i32(s, tcg_res, rd, pass, is_scalar ? size : 
MO_32);

WARNING: line over 80 characters
#78: FILE: target/arm/translate-a64.c:10973:
+                        /* As usual for ARM, separate negation for fused 
multiply-add */

WARNING: line over 80 characters
#81: FILE: target/arm/translate-a64.c:10976:
+                    gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, 
tcg_res, fpst);

WARNING: line over 80 characters
#85: FILE: target/arm/translate-a64.c:10980:
+                        /* As usual for ARM, separate negation for fused 
multiply-add */

WARNING: line over 80 characters
#88: FILE: target/arm/translate-a64.c:10983:
+                    gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, 
fpst);

WARNING: line over 80 characters
#102: FILE: target/arm/translate-a64.c:10993:
+                        gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx, 
fpst);

total: 0 errors, 7 warnings, 97 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 16/32: arm/translate-a64: add FP16 x2 ops for simd_indexed...
Checking PATCH 17/32: arm/translate-a64: initial decode for 
simd_two_reg_misc_fp16...
Checking PATCH 18/32: arm/translate-a64: add FP16 FPRINTx to 
simd_two_reg_misc_fp16...
Checking PATCH 19/32: arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16...
Checking PATCH 20/32: arm/translate-a64: add FP16 FCMxx (zero) to 
simd_two_reg_misc_fp16...
Checking PATCH 21/32: arm/translate-a64: add FP16 SCVTF/UCVFT to 
simd_two_reg_misc_fp16...
ERROR: space prohibited before that close parenthesis ')'
#25: FILE: target/arm/helper.c:10885:
+FLOAT_CONVS(si, h, 16, )

total: 1 errors, 0 warnings, 212 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 22/32: arm/translate-a64: add FP16 FNEG/FABS to 
simd_two_reg_misc_fp16...
Checking PATCH 23/32: arm/helper.c: re-factor recpe and add recepe_f16...
Checking PATCH 24/32: arm/translate-a64: add FP16 FRECPE...
Checking PATCH 25/32: arm/translate-a64: add FP16 FRCPX to 
simd_two_reg_misc_fp16...
Checking PATCH 26/32: arm/translate-a64: add FP16 FSQRT to 
simd_two_reg_misc_fp16...
Checking PATCH 27/32: arm/helper.c: re-factor rsqrte and add rsqrte_f16...
Checking PATCH 28/32: arm/translate-a64: add FP16 FRSQRTE to 
simd_two_reg_misc_fp16...
Checking PATCH 29/32: arm/translate-a64: add FP16 FMOV to simd_mod_imm...
Checking PATCH 30/32: arm/translate-a64: add all FP16 ops in 
simd_scalar_pairwise...
Checking PATCH 31/32: arm/translate-a64: implement 
simd_scalar_three_reg_same_fp16...
WARNING: line over 80 characters
#36: FILE: target/arm/translate-a64.c:7775:
+static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, uint32_t 
insn)

total: 0 errors, 1 warnings, 114 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 32/32: arm/translate-a64: add all single op FP16 to 
handle_fp_1src_half...
=== OUTPUT END ===

Test command exited with code: 1


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