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From: | Richard Henderson |
Subject: | Re: [Qemu-arm] [Qemu-devel] [PATCH v2 20/32] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 |
Date: | Thu, 8 Feb 2018 14:39:15 -0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/08/2018 09:31 AM, Alex Bennée wrote: > + maxpasses = hp ? (is_q ? 8 : 4) : (is_q ? 4 : 2); (8 << is_q) >> size ? > + read_vec_element_i32(s, tcg_op, rn, pass, hp ? MO_16 : MO_32); You already have size. > + return; > + break; Unreachable break. r~
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