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From: | Richard Henderson |
Subject: | Re: [Qemu-arm] [Qemu-devel] [PATCH v2 02/11] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling |
Date: | Fri, 9 Feb 2018 12:30:50 -0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/09/2018 08:58 AM, Peter Maydell wrote: > The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from > NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had > misimplemented this as making the bits RAZ/WI from both > Secure and NonSecure states. Fix this bug by checking > attrs.secure so that Secure code can pend and unpend NMIs. > > Signed-off-by: Peter Maydell <address@hidden> > --- > hw/intc/armv7m_nvic.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson <address@hidden> r~
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