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Re: [Qemu-arm] [PATCH v2 26/67] target/arm: Implement SVE Permute - Extr
From: |
Richard Henderson |
Subject: |
Re: [Qemu-arm] [PATCH v2 26/67] target/arm: Implement SVE Permute - Extract Group |
Date: |
Fri, 23 Feb 2018 09:46:47 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/23/2018 06:24 AM, Peter Maydell wrote:
> On 17 February 2018 at 18:22, Richard Henderson
> <address@hidden> wrote:
>> Signed-off-by: Richard Henderson <address@hidden>
>> ---
>> target/arm/helper-sve.h | 2 ++
>> target/arm/sve_helper.c | 81
>> ++++++++++++++++++++++++++++++++++++++++++++++
>> target/arm/translate-sve.c | 29 +++++++++++++++++
>> target/arm/sve.decode | 9 +++++-
>> 4 files changed, 120 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
>> index 79493ab647..94f4356ce9 100644
>> --- a/target/arm/helper-sve.h
>> +++ b/target/arm/helper-sve.h
>> @@ -414,6 +414,8 @@ DEF_HELPER_FLAGS_4(sve_cpy_z_h, TCG_CALL_NO_RWG, void,
>> ptr, ptr, i64, i32)
>> DEF_HELPER_FLAGS_4(sve_cpy_z_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
>> DEF_HELPER_FLAGS_4(sve_cpy_z_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
>>
>> +DEF_HELPER_FLAGS_4(sve_ext, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
>> +
>> DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
>> i32)
>> DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
>> i32)
>> DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
>> i32)
>> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
>> index 6a95d1ec48..fb3f54300b 100644
>> --- a/target/arm/sve_helper.c
>> +++ b/target/arm/sve_helper.c
>> @@ -1469,3 +1469,84 @@ void HELPER(sve_cpy_z_d)(void *vd, void *vg, uint64_t
>> val, uint32_t desc)
>> d[i] = (pg[H1(i)] & 1 ? val : 0);
>> }
>> }
>> +
>> +/* Big-endian hosts need to frob the byte indicies. If the copy
>> + * happens to be 8-byte aligned, then no frobbing necessary.
>> + */
>
> Have you run risu tests with a big endian host?
Some, early on. It's probably time to do it again.
Running those tests was why I dropped the ZIP/UZP/TRN patches from the host
vector support patch set. Supporting those endian agnostic is incompatible
with our "pdp-endian-like" storage of vectors for ARM -- we would have to put
the vectors in full host-endian order for that.
In the meantime, the frobbing within helpers does work.
r~
- [Qemu-arm] [PATCH v2 19/67] target/arm: Implement SVE Bitwise Shift - Unpredicated Group, (continued)
- [Qemu-arm] [PATCH v2 19/67] target/arm: Implement SVE Bitwise Shift - Unpredicated Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 22/67] target/arm: Implement SVE floating-point trig select coefficient, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 24/67] target/arm: Implement SVE Bitwise Immediate Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 23/67] target/arm: Implement SVE Element Count Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 26/67] target/arm: Implement SVE Permute - Extract Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 25/67] target/arm: Implement SVE Integer Wide Immediate - Predicated Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 28/67] target/arm: Implement SVE Permute - Predicates Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 27/67] target/arm: Implement SVE Permute - Unpredicated Group, Richard Henderson, 2018/02/17
- [Qemu-arm] [PATCH v2 30/67] target/arm: Implement SVE compress active elements, Richard Henderson, 2018/02/17