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[Qemu-arm] [RISU 1/3] Add aa64 sqrdml[as]h
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From: |
Richard Henderson |
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Subject: |
[Qemu-arm] [RISU 1/3] Add aa64 sqrdml[as]h |
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Date: |
Wed, 28 Feb 2018 08:48:13 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
aarch64.risu | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/aarch64.risu b/aarch64.risu
index 02e9183..c1a29f6 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -2932,6 +2932,30 @@ FCVTZUsi A64_V sf:1 0011110 type:2 1 11 001 000000 rn:5
rd:5 \
# UnallocatedEncoding: type >= 2
FCVTZUsi_RES A64_V sf:1 0011110 1 type:1 1 11 001 000000 rn:5 rd:5
+#
+# AdvSIMD v8.1 extensions
+#
+
address@hidden
+
+# SQRDMLAH (vector, scalar)
+SQRDMLAHvs A64_V81 01111110 size:2 0 rm:5 100001 rn:5 rd:5
+# SQRDMLAH (vector, vector)
+SQRDMLAHv A64_V81 0 q:1 101110 size:2 0 rm:5 100001 rn:5 rd:5
+# SQRDMLAH (element, scalar)
+SQRDMLAHse A64_V81 01111111 size:2 l:1 m:1 rm:4 1101 h:1 0 rn:5 rd:5
+# SQRDMLAH (element, vector)
+SQRDMLAHve A64_V81 0 q:1 101111 size:2 l:1 m:1 rm:4 1101 h:1 0 rn:5 rd:5
+
+# SQRDMLSH (vector, scalar)
+SQRDMLSHvs A64_V81 01111110 size:2 0 rm:5 100011 rn:5 rd:5
+# SQRDMLSH (vector, vector)
+SQRDMLSHv A64_V81 0 q:1 101110 size:2 0 rm:5 100011 rn:5 rd:5
+# SQRDMLSH (element, scalar)
+SQRDMLSHse A64_V81 01111111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5
+# SQRDMLSH (element, vector)
+SQRDMLSHve A64_V81 0 q:1 101111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5
+
@
# End of:
# Data processing - SIMD and floating point
--
2.14.3