Re: [Qemu-arm] [RISU PATCH v3 20/22] risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch

[Richard Henderson]

On 06/13/2018 02:55 AM, Alex Bennée wrote:
> +static void sve_dump_preg_diff(FILE *f, int vq,
> +                               uint16_t const (*p1)[SVE_VQ_MAX],
> +                               uint16_t const (*p2)[SVE_VQ_MAX])
> +{
> +    int q;
> +
> +    for (q = 0; q < vq; q++) {
> +       fprintf(f, "%#04x", *p1[q]);
> +    }
> +    fprintf(f, " vs ");
> +    for (q = 0; q < vq; q++) {
> +       fprintf(f, "%#04x", *p2[q]);

%# adds 0x into every 16-bit unit, so for vq=2 we get

  0xffff0xffff

Emit the 0x separately to start?

> +        for (i = 0; i < SVE_NUM_ZREGS; i++) {
> +           if (!sve_zreg_is_eq(m, a, i)) {
> +              int q;
> +              char *pad="";
> +              fprintf(f, "  Z%2d   : ", i);

%-2d?  %02d?

> +              for (q = 0; q < sve_vq_from_vl(ms->vl); q++) {
> +                 if (ms->zregs[i][q] != as->zregs[i][q]) {
> +                    fprintf(f, "%sq%02d: %016" PRIx64 "%016" PRIx64
> +                            " vs %016" PRIx64 "%016" PRIx64"\n", pad, q,

Actually, another thing that has annoyed me in the past,
but apparently not quite enough to actually fix, is the
fact that reginfo_dump and reginfo_dump_mismatch have a
slightly different format for Zregs.

It's probably worth splitting those bits out to helper
functions so that they must match.


r~