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[PATCH v4 07/16] tcg/aarch64: Reserve TCG_REG_TMP1, TCG_REG_TMP2
From: |
Richard Henderson |
Subject: |
[PATCH v4 07/16] tcg/aarch64: Reserve TCG_REG_TMP1, TCG_REG_TMP2 |
Date: |
Thu, 25 May 2023 17:23:25 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 8996e29ca9..5e7ac6fb76 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -40,11 +40,12 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
- TCG_REG_X16, TCG_REG_X17,
TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
+ /* X16 reserved as temporary */
+ /* X17 reserved as temporary */
/* X18 reserved by system */
/* X19 reserved for AREG0 */
/* X29 reserved as fp */
@@ -71,7 +72,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind
kind, int slot)
return TCG_REG_X0 + slot;
}
-#define TCG_REG_TMP0 TCG_REG_X30
+#define TCG_REG_TMP0 TCG_REG_X16
+#define TCG_REG_TMP1 TCG_REG_X17
+#define TCG_REG_TMP2 TCG_REG_X30
#define TCG_VEC_TMP0 TCG_REG_V31
#ifndef CONFIG_SOFTMMU
@@ -2902,6 +2905,8 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0);
}
--
2.34.1
- Re: [PATCH v4 02/16] accel/tcg: Fix check for page writeability in load_atomic16_or_exit, (continued)
[PATCH v4 01/16] tcg: Fix register move type in tcg_out_ld_helper_ret, Richard Henderson, 2023/05/25
[PATCH v4 03/16] meson: Split test for __int128_t type from __int128_t arithmetic, Richard Henderson, 2023/05/25
[PATCH v4 05/16] tcg/i386: Support 128-bit load/store, Richard Henderson, 2023/05/25
[PATCH v4 06/16] tcg/aarch64: Rename temporaries, Richard Henderson, 2023/05/25
[PATCH v4 04/16] qemu/atomic128: Add x86_64 atomic128-ldst.h, Richard Henderson, 2023/05/25
[PATCH v4 07/16] tcg/aarch64: Reserve TCG_REG_TMP1, TCG_REG_TMP2,
Richard Henderson <=
[PATCH v4 08/16] tcg/aarch64: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/05/25
[PATCH v4 12/16] accel/tcg: Extract load_atom_extract_al16_or_al8 to host header, Richard Henderson, 2023/05/25
[PATCH v4 10/16] tcg/ppc: Support 128-bit load/store, Richard Henderson, 2023/05/25
[PATCH v4 09/16] tcg/aarch64: Support 128-bit load/store, Richard Henderson, 2023/05/25
[PATCH v4 15/16] accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8, Richard Henderson, 2023/05/25
[PATCH v4 16/16] accel/tcg: Add aarch64 store_atom_insert_al16, Richard Henderson, 2023/05/25