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Re: [PATCH v2 01/20] target/arm: Add commentary for CPUARMState.exclusiv
From: |
Peter Maydell |
Subject: |
Re: [PATCH v2 01/20] target/arm: Add commentary for CPUARMState.exclusive_high |
Date: |
Tue, 30 May 2023 16:11:09 +0100 |
On Fri, 26 May 2023 at 15:44, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 5/26/23 02:49, Juan Quintela wrote:
> > Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
> >> Hi,
> >>
> >> On 26/5/23 01:25, Richard Henderson wrote:
> >>> Document the meaning of exclusive_high in a big-endian context,
> >>> and why we can't change it now.
> >>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >>> ---
> >>> target/arm/cpu.h | 7 +++++++
> >>> 1 file changed, 7 insertions(+)
> >>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> >>> index d469a2637b..4e16eab82e 100644
> >>> --- a/target/arm/cpu.h
> >>> +++ b/target/arm/cpu.h
> >>> @@ -677,8 +677,15 @@ typedef struct CPUArchState {
> >>> uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
> >>> uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
> >>> } vfp;
> >>> +
> >>> uint64_t exclusive_addr;
> >>> uint64_t exclusive_val;
> >>> + /*
> >>> + * Contains the 'val' for the second 64-bit register of LDXP, which
> >>> comes
> >>> + * from the higher address, not the high part of a complete 128-bit
> >>> value.
> >>> + * This is perhaps confusingly named, but the name is now baked into
> >>> the
> >>> + * migration format.
> >>> + */
> >>> uint64_t exclusive_high;
> >>
> >> Can't we rename the field if we add the old name to check_fields_match()
> >> in scripts/vmstate-static-checker.py?
> It's not worth any effort to rename. Just needed documentation.
Yeah; the important point here is "we can't trivially switch
to recording the exclusive value as 'high:low' of a guest
128 bit value" -- it has to remain "value from low address,
value from high address". Really what is baked into the
migration format is that the semantics of the two fields
are from-low-addr and from-high-addr.
If you replace this:
> >>> + * This is perhaps confusingly named, but the name is now baked into
> >>> the
> >>> + * migration format.
with:
* In some ways it might be more convenient to record the
* exclusive value as the low and high halves of a 128 bit
* data value, but the current semantics of these fields are
* baked into the migration format.
then:
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- Re: [PATCH v2 02/20] target/arm: Add feature test for FEAT_LSE2, (continued)
- [PATCH v2 05/20] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld}, Richard Henderson, 2023/05/25
- [PATCH v2 08/20] target/arm: Sink gen_mte_check1 into load/store_exclusive, Richard Henderson, 2023/05/25
- [PATCH v2 14/20] target/arm: Check alignment in helper_mte_check, Richard Henderson, 2023/05/25
- [PATCH v2 12/20] target/arm: Pass memop to gen_mte_check1*, Richard Henderson, 2023/05/25
- [PATCH v2 01/20] target/arm: Add commentary for CPUARMState.exclusive_high, Richard Henderson, 2023/05/25
[PATCH v2 20/20] target/arm: Enable FEAT_LSE2 for -cpu max, Richard Henderson, 2023/05/25
[PATCH v2 04/20] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP, Richard Henderson, 2023/05/25
[PATCH v2 13/20] target/arm: Pass single_memop to gen_mte_checkN, Richard Henderson, 2023/05/25
[PATCH v2 15/20] target/arm: Add SCTLR.nAA to TBFLAG_A64, Richard Henderson, 2023/05/25
[PATCH v2 16/20] target/arm: Relax ordered/atomic alignment checks for LSE2, Richard Henderson, 2023/05/25
[PATCH v2 17/20] target/arm: Move mte check for store-exclusive, Richard Henderson, 2023/05/25
[PATCH v2 19/20] tests/tcg/multiarch: Adjust sigbus.c, Richard Henderson, 2023/05/25
[PATCH v2 18/20] tests/tcg/aarch64: Use stz2g in mte-7.c, Richard Henderson, 2023/05/25