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[Qemu-commits] [qemu/qemu] 235eb0: target-mips: Add ASE DSP internal fun
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Subject: |
[Qemu-commits] [qemu/qemu] 235eb0: target-mips: Add ASE DSP internal functions |
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Date: |
Wed, 31 Oct 2012 15:00:17 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 235eb0158cfb31bb8a7cad7296e2327d7f7349fc
https://github.com/qemu/qemu/commit/235eb0158cfb31bb8a7cad7296e2327d7f7349fc
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/Makefile.objs
A target-mips/dsp_helper.c
Log Message:
-----------
target-mips: Add ASE DSP internal functions
Add internal functions using by MIPS ASE DSP instructions.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 853c3240c0753735b82fe80a86123e09234f5448
https://github.com/qemu/qemu/commit/853c3240c0753735b82fe80a86123e09234f5448
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M linux-user/main.c
M target-mips/cpu.h
M target-mips/helper.c
M target-mips/translate.c
Log Message:
-----------
target-mips: Add ASE DSP resources access check
Add MIPS ASE DSP resources access check.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 4133498f8e532f9a32dae2153ef5e14433626e9f
https://github.com/qemu/qemu/commit/4133498f8e532f9a32dae2153ef5e14433626e9f
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: e45a93e2590051e77a3d944a0feb3360a1ff1841
https://github.com/qemu/qemu/commit/e45a93e2590051e77a3d944a0feb3360a1ff1841
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: Add ASE DSP branch instructions
Add MIPS ASE DSP Branch instructions.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 9b1a1d68d0411cf67502b2adb3daae2eb157b704
https://github.com/qemu/qemu/commit/9b1a1d68d0411cf67502b2adb3daae2eb157b704
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: Add ASE DSP load instructions
Add MIPS ASE DSP Load instructions.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 461c08df75d8564a3ef8582bfcda398e9b09c0ff
https://github.com/qemu/qemu/commit/461c08df75d8564a3ef8582bfcda398e9b09c0ff
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/dsp_helper.c
M target-mips/helper.h
M target-mips/translate.c
Log Message:
-----------
target-mips: Add ASE DSP arithmetic instructions
Add MIPS ASE DSP Arithmetic instructions.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 77c5fa8b55adbd277dfa272752b4e99836ee4702
https://github.com/qemu/qemu/commit/77c5fa8b55adbd277dfa272752b4e99836ee4702
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/dsp_helper.c
M target-mips/helper.h
M target-mips/translate.c
Log Message:
-----------
target-mips: Add ASE DSP GPR-based shift instructions
Add MIPS ASE DSP GPR-Based Shift instructions.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: a22260ae380fa6abb546479cfc2962ba4c40382d
https://github.com/qemu/qemu/commit/a22260ae380fa6abb546479cfc2962ba4c40382d
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/dsp_helper.c
M target-mips/helper.h
M target-mips/translate.c
Log Message:
-----------
target-mips: Add ASE DSP multiply instructions
Add MIPS ASE DSP Multiply instructions.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 1cb6686cf926e0efc2056405a0a76dd41eb65d89
https://github.com/qemu/qemu/commit/1cb6686cf926e0efc2056405a0a76dd41eb65d89
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/dsp_helper.c
M target-mips/helper.h
M target-mips/translate.c
Log Message:
-----------
target-mips: Add ASE DSP bit/manipulation instructions
Add MIPS ASE DSP Bit/Manipulation instructions.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 266905602401e4aa849372bc50a71b2987157727
https://github.com/qemu/qemu/commit/266905602401e4aa849372bc50a71b2987157727
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/dsp_helper.c
M target-mips/helper.h
M target-mips/translate.c
Log Message:
-----------
target-mips: Add ASE DSP compare-pick instructions
Add MIPS ASE DSP Compare-Pick instructions.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: b53371ed5d4b6a678bf524d381f80746739b7fc0
https://github.com/qemu/qemu/commit/b53371ed5d4b6a678bf524d381f80746739b7fc0
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/dsp_helper.c
M target-mips/helper.h
M target-mips/translate.c
Log Message:
-----------
target-mips: Add ASE DSP accumulator instructions
Add MIPS ASE DSP Accumulator and DSPControl Access instructions.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: af13ae03f8dbc02974d53b11b80b3ae4dd9f30b4
https://github.com/qemu/qemu/commit/af13ae03f8dbc02974d53b11b80b3ae4dd9f30b4
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate_init.c
Log Message:
-----------
target-mips: Add ASE DSP processors
Add 74kf and mips64dspr2-generic-cpu model for test.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: d70080c4e37fc533fa10904b286f29449decc6f8
https://github.com/qemu/qemu/commit/d70080c4e37fc533fa10904b286f29449decc6f8
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
A tests/tcg/mips/mips32-dsp/Makefile
A tests/tcg/mips/mips32-dsp/absq_s_ph.c
A tests/tcg/mips/mips32-dsp/absq_s_w.c
A tests/tcg/mips/mips32-dsp/addq_ph.c
A tests/tcg/mips/mips32-dsp/addq_s_ph.c
A tests/tcg/mips/mips32-dsp/addq_s_w.c
A tests/tcg/mips/mips32-dsp/addsc.c
A tests/tcg/mips/mips32-dsp/addu_qb.c
A tests/tcg/mips/mips32-dsp/addu_s_qb.c
A tests/tcg/mips/mips32-dsp/addwc.c
A tests/tcg/mips/mips32-dsp/bitrev.c
A tests/tcg/mips/mips32-dsp/bposge32.c
A tests/tcg/mips/mips32-dsp/cmp_eq_ph.c
A tests/tcg/mips/mips32-dsp/cmp_le_ph.c
A tests/tcg/mips/mips32-dsp/cmp_lt_ph.c
A tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c
A tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c
A tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c
A tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c
A tests/tcg/mips/mips32-dsp/cmpu_le_qb.c
A tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c
A tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c
A tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c
A tests/tcg/mips/mips32-dsp/dpau_h_qbl.c
A tests/tcg/mips/mips32-dsp/dpau_h_qbr.c
A tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c
A tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c
A tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c
A tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c
A tests/tcg/mips/mips32-dsp/extp.c
A tests/tcg/mips/mips32-dsp/extpdp.c
A tests/tcg/mips/mips32-dsp/extpdpv.c
A tests/tcg/mips/mips32-dsp/extpv.c
A tests/tcg/mips/mips32-dsp/extr_r_w.c
A tests/tcg/mips/mips32-dsp/extr_rs_w.c
A tests/tcg/mips/mips32-dsp/extr_s_h.c
A tests/tcg/mips/mips32-dsp/extr_w.c
A tests/tcg/mips/mips32-dsp/extrv_r_w.c
A tests/tcg/mips/mips32-dsp/extrv_rs_w.c
A tests/tcg/mips/mips32-dsp/extrv_s_h.c
A tests/tcg/mips/mips32-dsp/extrv_w.c
A tests/tcg/mips/mips32-dsp/insv.c
A tests/tcg/mips/mips32-dsp/lbux.c
A tests/tcg/mips/mips32-dsp/lhx.c
A tests/tcg/mips/mips32-dsp/lwx.c
A tests/tcg/mips/mips32-dsp/madd.c
A tests/tcg/mips/mips32-dsp/maddu.c
A tests/tcg/mips/mips32-dsp/main.c
A tests/tcg/mips/mips32-dsp/maq_s_w_phl.c
A tests/tcg/mips/mips32-dsp/maq_s_w_phr.c
A tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c
A tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c
A tests/tcg/mips/mips32-dsp/mfhi.c
A tests/tcg/mips/mips32-dsp/mflo.c
A tests/tcg/mips/mips32-dsp/modsub.c
A tests/tcg/mips/mips32-dsp/msub.c
A tests/tcg/mips/mips32-dsp/msubu.c
A tests/tcg/mips/mips32-dsp/mthi.c
A tests/tcg/mips/mips32-dsp/mthlip.c
A tests/tcg/mips/mips32-dsp/mtlo.c
A tests/tcg/mips/mips32-dsp/muleq_s_w_phl.c
A tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c
A tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c
A tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c
A tests/tcg/mips/mips32-dsp/mulq_rs_ph.c
A tests/tcg/mips/mips32-dsp/mult.c
A tests/tcg/mips/mips32-dsp/multu.c
A tests/tcg/mips/mips32-dsp/packrl_ph.c
A tests/tcg/mips/mips32-dsp/pick_ph.c
A tests/tcg/mips/mips32-dsp/pick_qb.c
A tests/tcg/mips/mips32-dsp/preceq_w_phl.c
A tests/tcg/mips/mips32-dsp/preceq_w_phr.c
A tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c
A tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c
A tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c
A tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c
A tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c
A tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c
A tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c
A tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c
A tests/tcg/mips/mips32-dsp/precrq_ph_w.c
A tests/tcg/mips/mips32-dsp/precrq_qb_ph.c
A tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c
A tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c
A tests/tcg/mips/mips32-dsp/raddu_w_qb.c
A tests/tcg/mips/mips32-dsp/rddsp.c
A tests/tcg/mips/mips32-dsp/repl_ph.c
A tests/tcg/mips/mips32-dsp/repl_qb.c
A tests/tcg/mips/mips32-dsp/replv_ph.c
A tests/tcg/mips/mips32-dsp/replv_qb.c
A tests/tcg/mips/mips32-dsp/shilo.c
A tests/tcg/mips/mips32-dsp/shilov.c
A tests/tcg/mips/mips32-dsp/shll_ph.c
A tests/tcg/mips/mips32-dsp/shll_qb.c
A tests/tcg/mips/mips32-dsp/shll_s_ph.c
A tests/tcg/mips/mips32-dsp/shll_s_w.c
A tests/tcg/mips/mips32-dsp/shllv_ph.c
A tests/tcg/mips/mips32-dsp/shllv_qb.c
A tests/tcg/mips/mips32-dsp/shllv_s_ph.c
A tests/tcg/mips/mips32-dsp/shllv_s_w.c
A tests/tcg/mips/mips32-dsp/shra_ph.c
A tests/tcg/mips/mips32-dsp/shra_r_ph.c
A tests/tcg/mips/mips32-dsp/shra_r_w.c
A tests/tcg/mips/mips32-dsp/shrav_ph.c
A tests/tcg/mips/mips32-dsp/shrav_r_ph.c
A tests/tcg/mips/mips32-dsp/shrav_r_w.c
A tests/tcg/mips/mips32-dsp/shrl_qb.c
A tests/tcg/mips/mips32-dsp/shrlv_qb.c
A tests/tcg/mips/mips32-dsp/subq_ph.c
A tests/tcg/mips/mips32-dsp/subq_s_ph.c
A tests/tcg/mips/mips32-dsp/subq_s_w.c
A tests/tcg/mips/mips32-dsp/subu_qb.c
A tests/tcg/mips/mips32-dsp/subu_s_qb.c
A tests/tcg/mips/mips32-dsp/wrdsp.c
A tests/tcg/mips/mips32-dspr2/Makefile
A tests/tcg/mips/mips32-dspr2/absq_s_qb.c
A tests/tcg/mips/mips32-dspr2/addqh_ph.c
A tests/tcg/mips/mips32-dspr2/addqh_r_ph.c
A tests/tcg/mips/mips32-dspr2/addqh_r_w.c
A tests/tcg/mips/mips32-dspr2/addqh_w.c
A tests/tcg/mips/mips32-dspr2/addu_ph.c
A tests/tcg/mips/mips32-dspr2/addu_s_ph.c
A tests/tcg/mips/mips32-dspr2/adduh_qb.c
A tests/tcg/mips/mips32-dspr2/adduh_r_qb.c
A tests/tcg/mips/mips32-dspr2/append.c
A tests/tcg/mips/mips32-dspr2/balign.c
A tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c
A tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c
A tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c
A tests/tcg/mips/mips32-dspr2/dpa_w_ph.c
A tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c
A tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c
A tests/tcg/mips/mips32-dspr2/dpax_w_ph.c
A tests/tcg/mips/mips32-dspr2/dps_w_ph.c
A tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c
A tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c
A tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c
A tests/tcg/mips/mips32-dspr2/mul_ph.c
A tests/tcg/mips/mips32-dspr2/mul_s_ph.c
A tests/tcg/mips/mips32-dspr2/mulq_rs_w.c
A tests/tcg/mips/mips32-dspr2/mulq_s_ph.c
A tests/tcg/mips/mips32-dspr2/mulq_s_w.c
A tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c
A tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c
A tests/tcg/mips/mips32-dspr2/precr_qb_ph.c
A tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c
A tests/tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c
A tests/tcg/mips/mips32-dspr2/prepend.c
A tests/tcg/mips/mips32-dspr2/shra_qb.c
A tests/tcg/mips/mips32-dspr2/shra_r_qb.c
A tests/tcg/mips/mips32-dspr2/shrav_qb.c
A tests/tcg/mips/mips32-dspr2/shrav_r_qb.c
A tests/tcg/mips/mips32-dspr2/shrl_ph.c
A tests/tcg/mips/mips32-dspr2/shrlv_ph.c
A tests/tcg/mips/mips32-dspr2/subqh_ph.c
A tests/tcg/mips/mips32-dspr2/subqh_r_ph.c
A tests/tcg/mips/mips32-dspr2/subqh_r_w.c
A tests/tcg/mips/mips32-dspr2/subqh_w.c
A tests/tcg/mips/mips32-dspr2/subu_ph.c
A tests/tcg/mips/mips32-dspr2/subu_s_ph.c
A tests/tcg/mips/mips32-dspr2/subuh_qb.c
A tests/tcg/mips/mips32-dspr2/subuh_r_qb.c
A tests/tcg/mips/mips64-dsp/Makefile
A tests/tcg/mips/mips64-dsp/absq_s_ob.c
A tests/tcg/mips/mips64-dsp/absq_s_ph.c
A tests/tcg/mips/mips64-dsp/absq_s_pw.c
A tests/tcg/mips/mips64-dsp/absq_s_qh.c
A tests/tcg/mips/mips64-dsp/absq_s_w.c
A tests/tcg/mips/mips64-dsp/addq_ph.c
A tests/tcg/mips/mips64-dsp/addq_pw.c
A tests/tcg/mips/mips64-dsp/addq_qh.c
A tests/tcg/mips/mips64-dsp/addq_s_ph.c
A tests/tcg/mips/mips64-dsp/addq_s_pw.c
A tests/tcg/mips/mips64-dsp/addq_s_qh.c
A tests/tcg/mips/mips64-dsp/addq_s_w.c
A tests/tcg/mips/mips64-dsp/addsc.c
A tests/tcg/mips/mips64-dsp/addu_ob.c
A tests/tcg/mips/mips64-dsp/addu_qb.c
A tests/tcg/mips/mips64-dsp/addu_s_ob.c
A tests/tcg/mips/mips64-dsp/addu_s_qb.c
A tests/tcg/mips/mips64-dsp/addwc.c
A tests/tcg/mips/mips64-dsp/bitrev.c
A tests/tcg/mips/mips64-dsp/bposge32.c
A tests/tcg/mips/mips64-dsp/bposge64.c
A tests/tcg/mips/mips64-dsp/cmp_eq_ph.c
A tests/tcg/mips/mips64-dsp/cmp_eq_pw.c
A tests/tcg/mips/mips64-dsp/cmp_eq_qh.c
A tests/tcg/mips/mips64-dsp/cmp_le_ph.c
A tests/tcg/mips/mips64-dsp/cmp_le_pw.c
A tests/tcg/mips/mips64-dsp/cmp_le_qh.c
A tests/tcg/mips/mips64-dsp/cmp_lt_ph.c
A tests/tcg/mips/mips64-dsp/cmp_lt_pw.c
A tests/tcg/mips/mips64-dsp/cmp_lt_qh.c
A tests/tcg/mips/mips64-dsp/cmpgu_eq_ob.c
A tests/tcg/mips/mips64-dsp/cmpgu_eq_qb.c
A tests/tcg/mips/mips64-dsp/cmpgu_le_ob.c
A tests/tcg/mips/mips64-dsp/cmpgu_le_qb.c
A tests/tcg/mips/mips64-dsp/cmpgu_lt_ob.c
A tests/tcg/mips/mips64-dsp/cmpgu_lt_qb.c
A tests/tcg/mips/mips64-dsp/cmpu_eq_ob.c
A tests/tcg/mips/mips64-dsp/cmpu_eq_qb.c
A tests/tcg/mips/mips64-dsp/cmpu_le_ob.c
A tests/tcg/mips/mips64-dsp/cmpu_le_qb.c
A tests/tcg/mips/mips64-dsp/cmpu_lt_ob.c
A tests/tcg/mips/mips64-dsp/cmpu_lt_qb.c
A tests/tcg/mips/mips64-dsp/dappend.c
A tests/tcg/mips/mips64-dsp/dextp.c
A tests/tcg/mips/mips64-dsp/dextpdp.c
A tests/tcg/mips/mips64-dsp/dextpdpv.c
A tests/tcg/mips/mips64-dsp/dextpv.c
A tests/tcg/mips/mips64-dsp/dextr_l.c
A tests/tcg/mips/mips64-dsp/dextr_r_l.c
A tests/tcg/mips/mips64-dsp/dextr_r_w.c
A tests/tcg/mips/mips64-dsp/dextr_rs_l.c
A tests/tcg/mips/mips64-dsp/dextr_rs_w.c
A tests/tcg/mips/mips64-dsp/dextr_s_h.c
A tests/tcg/mips/mips64-dsp/dextr_w.c
A tests/tcg/mips/mips64-dsp/dextrv_l.c
A tests/tcg/mips/mips64-dsp/dextrv_r_l.c
A tests/tcg/mips/mips64-dsp/dextrv_r_w.c
A tests/tcg/mips/mips64-dsp/dextrv_rs_l.c
A tests/tcg/mips/mips64-dsp/dextrv_rs_w.c
A tests/tcg/mips/mips64-dsp/dextrv_s_h.c
A tests/tcg/mips/mips64-dsp/dextrv_w.c
A tests/tcg/mips/mips64-dsp/dinsv.c
A tests/tcg/mips/mips64-dsp/dmadd.c
A tests/tcg/mips/mips64-dsp/dmaddu.c
A tests/tcg/mips/mips64-dsp/dmsub.c
A tests/tcg/mips/mips64-dsp/dmsubu.c
A tests/tcg/mips/mips64-dsp/dmthlip.c
A tests/tcg/mips/mips64-dsp/dpaq_s_w_ph.c
A tests/tcg/mips/mips64-dsp/dpaq_s_w_qh.c
A tests/tcg/mips/mips64-dsp/dpaq_sa_l_pw.c
A tests/tcg/mips/mips64-dsp/dpaq_sa_l_w.c
A tests/tcg/mips/mips64-dsp/dpau_h_obl.c
A tests/tcg/mips/mips64-dsp/dpau_h_obr.c
A tests/tcg/mips/mips64-dsp/dpau_h_qbl.c
A tests/tcg/mips/mips64-dsp/dpau_h_qbr.c
A tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c
A tests/tcg/mips/mips64-dsp/dpsq_s_w_qh.c
A tests/tcg/mips/mips64-dsp/dpsq_sa_l_pw.c
A tests/tcg/mips/mips64-dsp/dpsq_sa_l_w.c
A tests/tcg/mips/mips64-dsp/dpsu_h_obl.c
A tests/tcg/mips/mips64-dsp/dpsu_h_obr.c
A tests/tcg/mips/mips64-dsp/dpsu_h_qbl.c
A tests/tcg/mips/mips64-dsp/dpsu_h_qbr.c
A tests/tcg/mips/mips64-dsp/dshilo.c
A tests/tcg/mips/mips64-dsp/dshilov.c
A tests/tcg/mips/mips64-dsp/extp.c
A tests/tcg/mips/mips64-dsp/extpdp.c
A tests/tcg/mips/mips64-dsp/extpdpv.c
A tests/tcg/mips/mips64-dsp/extpv.c
A tests/tcg/mips/mips64-dsp/extr_r_w.c
A tests/tcg/mips/mips64-dsp/extr_rs_w.c
A tests/tcg/mips/mips64-dsp/extr_s_h.c
A tests/tcg/mips/mips64-dsp/extr_w.c
A tests/tcg/mips/mips64-dsp/extrv_r_w.c
A tests/tcg/mips/mips64-dsp/extrv_rs_w.c
A tests/tcg/mips/mips64-dsp/extrv_s_h.c
A tests/tcg/mips/mips64-dsp/extrv_w.c
A tests/tcg/mips/mips64-dsp/head.S
A tests/tcg/mips/mips64-dsp/insv.c
A tests/tcg/mips/mips64-dsp/io.h
A tests/tcg/mips/mips64-dsp/lbux.c
A tests/tcg/mips/mips64-dsp/ldx.c
A tests/tcg/mips/mips64-dsp/lhx.c
A tests/tcg/mips/mips64-dsp/lwx.c
A tests/tcg/mips/mips64-dsp/madd.c
A tests/tcg/mips/mips64-dsp/maddu.c
A tests/tcg/mips/mips64-dsp/maq_s_l_pwl.c
A tests/tcg/mips/mips64-dsp/maq_s_l_pwr.c
A tests/tcg/mips/mips64-dsp/maq_s_w_phl.c
A tests/tcg/mips/mips64-dsp/maq_s_w_phr.c
A tests/tcg/mips/mips64-dsp/maq_s_w_qhll.c
A tests/tcg/mips/mips64-dsp/maq_s_w_qhlr.c
A tests/tcg/mips/mips64-dsp/maq_s_w_qhrl.c
A tests/tcg/mips/mips64-dsp/maq_s_w_qhrr.c
A tests/tcg/mips/mips64-dsp/maq_sa_w_phl.c
A tests/tcg/mips/mips64-dsp/maq_sa_w_phr.c
A tests/tcg/mips/mips64-dsp/maq_sa_w_qhll.c
A tests/tcg/mips/mips64-dsp/maq_sa_w_qhlr.c
A tests/tcg/mips/mips64-dsp/maq_sa_w_qhrl.c
A tests/tcg/mips/mips64-dsp/maq_sa_w_qhrr.c
A tests/tcg/mips/mips64-dsp/mfhi.c
A tests/tcg/mips/mips64-dsp/mflo.c
A tests/tcg/mips/mips64-dsp/mips_boot.lds
A tests/tcg/mips/mips64-dsp/modsub.c
A tests/tcg/mips/mips64-dsp/msub.c
A tests/tcg/mips/mips64-dsp/msubu.c
A tests/tcg/mips/mips64-dsp/mthi.c
A tests/tcg/mips/mips64-dsp/mthlip.c
A tests/tcg/mips/mips64-dsp/mtlo.c
A tests/tcg/mips/mips64-dsp/muleq_s_pw_qhl.c
A tests/tcg/mips/mips64-dsp/muleq_s_pw_qhr.c
A tests/tcg/mips/mips64-dsp/muleq_s_w_phl.c
A tests/tcg/mips/mips64-dsp/muleq_s_w_phr.c
A tests/tcg/mips/mips64-dsp/muleu_s_ph_qbl.c
A tests/tcg/mips/mips64-dsp/muleu_s_ph_qbr.c
A tests/tcg/mips/mips64-dsp/muleu_s_qh_obl.c
A tests/tcg/mips/mips64-dsp/muleu_s_qh_obr.c
A tests/tcg/mips/mips64-dsp/mulq_rs_ph.c
A tests/tcg/mips/mips64-dsp/mulq_rs_qh.c
A tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c
A tests/tcg/mips/mips64-dsp/mulsaq_s_w_qh.c
A tests/tcg/mips/mips64-dsp/mult.c
A tests/tcg/mips/mips64-dsp/multu.c
A tests/tcg/mips/mips64-dsp/packrl_ph.c
A tests/tcg/mips/mips64-dsp/packrl_pw.c
A tests/tcg/mips/mips64-dsp/pick_ob.c
A tests/tcg/mips/mips64-dsp/pick_ph.c
A tests/tcg/mips/mips64-dsp/pick_pw.c
A tests/tcg/mips/mips64-dsp/pick_qb.c
A tests/tcg/mips/mips64-dsp/pick_qh.c
A tests/tcg/mips/mips64-dsp/preceq_l_pwl.c
A tests/tcg/mips/mips64-dsp/preceq_l_pwr.c
A tests/tcg/mips/mips64-dsp/preceq_pw_qhl.c
A tests/tcg/mips/mips64-dsp/preceq_pw_qhla.c
A tests/tcg/mips/mips64-dsp/preceq_pw_qhr.c
A tests/tcg/mips/mips64-dsp/preceq_pw_qhra.c
A tests/tcg/mips/mips64-dsp/preceq_w_phl.c
A tests/tcg/mips/mips64-dsp/preceq_w_phr.c
A tests/tcg/mips/mips64-dsp/precequ_ph_qbl.c
A tests/tcg/mips/mips64-dsp/precequ_ph_qbla.c
A tests/tcg/mips/mips64-dsp/precequ_ph_qbr.c
A tests/tcg/mips/mips64-dsp/precequ_ph_qbra.c
A tests/tcg/mips/mips64-dsp/precequ_qh_obl.c
A tests/tcg/mips/mips64-dsp/precequ_qh_obla.c
A tests/tcg/mips/mips64-dsp/precequ_qh_obr.c
A tests/tcg/mips/mips64-dsp/precequ_qh_obra.c
A tests/tcg/mips/mips64-dsp/preceu_ph_qbl.c
A tests/tcg/mips/mips64-dsp/preceu_ph_qbla.c
A tests/tcg/mips/mips64-dsp/preceu_ph_qbr.c
A tests/tcg/mips/mips64-dsp/preceu_ph_qbra.c
A tests/tcg/mips/mips64-dsp/preceu_qh_obl.c
A tests/tcg/mips/mips64-dsp/preceu_qh_obla.c
A tests/tcg/mips/mips64-dsp/preceu_qh_obr.c
A tests/tcg/mips/mips64-dsp/preceu_qh_obra.c
A tests/tcg/mips/mips64-dsp/precr_ob_qh.c
A tests/tcg/mips/mips64-dsp/precr_sra_qh_pw.c
A tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c
A tests/tcg/mips/mips64-dsp/precrq_ob_qh.c
A tests/tcg/mips/mips64-dsp/precrq_ph_w.c
A tests/tcg/mips/mips64-dsp/precrq_pw_l.c
A tests/tcg/mips/mips64-dsp/precrq_qb_ph.c
A tests/tcg/mips/mips64-dsp/precrq_qh_pw.c
A tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c
A tests/tcg/mips/mips64-dsp/precrq_rs_qh_pw.c
A tests/tcg/mips/mips64-dsp/precrqu_s_ob_qh.c
A tests/tcg/mips/mips64-dsp/precrqu_s_qb_ph.c
A tests/tcg/mips/mips64-dsp/prependd.c
A tests/tcg/mips/mips64-dsp/prependw.c
A tests/tcg/mips/mips64-dsp/printf.c
A tests/tcg/mips/mips64-dsp/raddu_l_ob.c
A tests/tcg/mips/mips64-dsp/raddu_w_qb.c
A tests/tcg/mips/mips64-dsp/rddsp.c
A tests/tcg/mips/mips64-dsp/repl_ob.c
A tests/tcg/mips/mips64-dsp/repl_ph.c
A tests/tcg/mips/mips64-dsp/repl_pw.c
A tests/tcg/mips/mips64-dsp/repl_qb.c
A tests/tcg/mips/mips64-dsp/repl_qh.c
A tests/tcg/mips/mips64-dsp/replv_ob.c
A tests/tcg/mips/mips64-dsp/replv_ph.c
A tests/tcg/mips/mips64-dsp/replv_pw.c
A tests/tcg/mips/mips64-dsp/replv_qb.c
A tests/tcg/mips/mips64-dsp/shilo.c
A tests/tcg/mips/mips64-dsp/shilov.c
A tests/tcg/mips/mips64-dsp/shll_ob.c
A tests/tcg/mips/mips64-dsp/shll_ph.c
A tests/tcg/mips/mips64-dsp/shll_pw.c
A tests/tcg/mips/mips64-dsp/shll_qb.c
A tests/tcg/mips/mips64-dsp/shll_qh.c
A tests/tcg/mips/mips64-dsp/shll_s_ph.c
A tests/tcg/mips/mips64-dsp/shll_s_pw.c
A tests/tcg/mips/mips64-dsp/shll_s_qh.c
A tests/tcg/mips/mips64-dsp/shll_s_w.c
A tests/tcg/mips/mips64-dsp/shllv_ob.c
A tests/tcg/mips/mips64-dsp/shllv_ph.c
A tests/tcg/mips/mips64-dsp/shllv_pw.c
A tests/tcg/mips/mips64-dsp/shllv_qb.c
A tests/tcg/mips/mips64-dsp/shllv_qh.c
A tests/tcg/mips/mips64-dsp/shllv_s_ph.c
A tests/tcg/mips/mips64-dsp/shllv_s_pw.c
A tests/tcg/mips/mips64-dsp/shllv_s_qh.c
A tests/tcg/mips/mips64-dsp/shllv_s_w.c
A tests/tcg/mips/mips64-dsp/shra_ob.c
A tests/tcg/mips/mips64-dsp/shra_ph.c
A tests/tcg/mips/mips64-dsp/shra_pw.c
A tests/tcg/mips/mips64-dsp/shra_qh.c
A tests/tcg/mips/mips64-dsp/shra_r_ob.c
A tests/tcg/mips/mips64-dsp/shra_r_ph.c
A tests/tcg/mips/mips64-dsp/shra_r_pw.c
A tests/tcg/mips/mips64-dsp/shra_r_qh.c
A tests/tcg/mips/mips64-dsp/shra_r_w.c
A tests/tcg/mips/mips64-dsp/shrav_ph.c
A tests/tcg/mips/mips64-dsp/shrav_pw.c
A tests/tcg/mips/mips64-dsp/shrav_qh.c
A tests/tcg/mips/mips64-dsp/shrav_r_ph.c
A tests/tcg/mips/mips64-dsp/shrav_r_pw.c
A tests/tcg/mips/mips64-dsp/shrav_r_qh.c
A tests/tcg/mips/mips64-dsp/shrav_r_w.c
A tests/tcg/mips/mips64-dsp/shrl_ob.c
A tests/tcg/mips/mips64-dsp/shrl_qb.c
A tests/tcg/mips/mips64-dsp/shrl_qh.c
A tests/tcg/mips/mips64-dsp/shrlv_ob.c
A tests/tcg/mips/mips64-dsp/shrlv_qb.c
A tests/tcg/mips/mips64-dsp/shrlv_qh.c
A tests/tcg/mips/mips64-dsp/subq_ph.c
A tests/tcg/mips/mips64-dsp/subq_pw.c
A tests/tcg/mips/mips64-dsp/subq_qh.c
A tests/tcg/mips/mips64-dsp/subq_s_ph.c
A tests/tcg/mips/mips64-dsp/subq_s_pw.c
A tests/tcg/mips/mips64-dsp/subq_s_qh.c
A tests/tcg/mips/mips64-dsp/subq_s_w.c
A tests/tcg/mips/mips64-dsp/subu_ob.c
A tests/tcg/mips/mips64-dsp/subu_qb.c
A tests/tcg/mips/mips64-dsp/subu_s_ob.c
A tests/tcg/mips/mips64-dsp/subu_s_qb.c
A tests/tcg/mips/mips64-dsp/wrdsp.c
A tests/tcg/mips/mips64-dspr2/.directory
A tests/tcg/mips/mips64-dspr2/Makefile
A tests/tcg/mips/mips64-dspr2/absq_s_qb.c
A tests/tcg/mips/mips64-dspr2/addqh_ph.c
A tests/tcg/mips/mips64-dspr2/addqh_r_ph.c
A tests/tcg/mips/mips64-dspr2/addqh_r_w.c
A tests/tcg/mips/mips64-dspr2/addqh_w.c
A tests/tcg/mips/mips64-dspr2/addu_ph.c
A tests/tcg/mips/mips64-dspr2/addu_qh.c
A tests/tcg/mips/mips64-dspr2/addu_s_ph.c
A tests/tcg/mips/mips64-dspr2/addu_s_qh.c
A tests/tcg/mips/mips64-dspr2/adduh_ob.c
A tests/tcg/mips/mips64-dspr2/adduh_qb.c
A tests/tcg/mips/mips64-dspr2/adduh_r_ob.c
A tests/tcg/mips/mips64-dspr2/adduh_r_qb.c
A tests/tcg/mips/mips64-dspr2/append.c
A tests/tcg/mips/mips64-dspr2/balign.c
A tests/tcg/mips/mips64-dspr2/cmpgdu_eq_ob.c
A tests/tcg/mips/mips64-dspr2/cmpgdu_eq_qb.c
A tests/tcg/mips/mips64-dspr2/cmpgdu_le_ob.c
A tests/tcg/mips/mips64-dspr2/cmpgdu_le_qb.c
A tests/tcg/mips/mips64-dspr2/cmpgdu_lt_ob.c
A tests/tcg/mips/mips64-dspr2/cmpgdu_lt_qb.c
A tests/tcg/mips/mips64-dspr2/dbalign.c
A tests/tcg/mips/mips64-dspr2/dpa_w_ph.c
A tests/tcg/mips/mips64-dspr2/dpa_w_qh.c
A tests/tcg/mips/mips64-dspr2/dpaqx_s_w_ph.c
A tests/tcg/mips/mips64-dspr2/dpaqx_sa_w_ph.c
A tests/tcg/mips/mips64-dspr2/dpax_w_ph.c
A tests/tcg/mips/mips64-dspr2/dps_w_ph.c
A tests/tcg/mips/mips64-dspr2/dps_w_qh.c
A tests/tcg/mips/mips64-dspr2/dpsqx_s_w_ph.c
A tests/tcg/mips/mips64-dspr2/dpsqx_sa_w_ph.c
A tests/tcg/mips/mips64-dspr2/dpsx_w_ph.c
A tests/tcg/mips/mips64-dspr2/head.S
A tests/tcg/mips/mips64-dspr2/io.h
A tests/tcg/mips/mips64-dspr2/mips_boot.lds
A tests/tcg/mips/mips64-dspr2/mul_ph.c
A tests/tcg/mips/mips64-dspr2/mul_s_ph.c
A tests/tcg/mips/mips64-dspr2/mulq_rs_w.c
A tests/tcg/mips/mips64-dspr2/mulq_s_ph.c
A tests/tcg/mips/mips64-dspr2/mulq_s_w.c
A tests/tcg/mips/mips64-dspr2/mulsa_w_ph.c
A tests/tcg/mips/mips64-dspr2/mulsaq_s_w_ph.c
A tests/tcg/mips/mips64-dspr2/precr_qb_ph.c
A tests/tcg/mips/mips64-dspr2/precr_sra_ph_w.c
A tests/tcg/mips/mips64-dspr2/precr_sra_r_ph_w.c
A tests/tcg/mips/mips64-dspr2/prepend.c
A tests/tcg/mips/mips64-dspr2/printf.c
A tests/tcg/mips/mips64-dspr2/shra_qb.c
A tests/tcg/mips/mips64-dspr2/shra_r_qb.c
A tests/tcg/mips/mips64-dspr2/shrav_ob.c
A tests/tcg/mips/mips64-dspr2/shrav_qb.c
A tests/tcg/mips/mips64-dspr2/shrav_r_ob.c
A tests/tcg/mips/mips64-dspr2/shrav_r_qb.c
A tests/tcg/mips/mips64-dspr2/shrl_ph.c
A tests/tcg/mips/mips64-dspr2/shrlv_ph.c
A tests/tcg/mips/mips64-dspr2/subqh_ph.c
A tests/tcg/mips/mips64-dspr2/subqh_r_ph.c
A tests/tcg/mips/mips64-dspr2/subqh_r_w.c
A tests/tcg/mips/mips64-dspr2/subqh_w.c
A tests/tcg/mips/mips64-dspr2/subu_ph.c
A tests/tcg/mips/mips64-dspr2/subu_qh.c
A tests/tcg/mips/mips64-dspr2/subu_s_ph.c
A tests/tcg/mips/mips64-dspr2/subu_s_qh.c
A tests/tcg/mips/mips64-dspr2/subuh_ob.c
A tests/tcg/mips/mips64-dspr2/subuh_qb.c
A tests/tcg/mips/mips64-dspr2/subuh_r_ob.c
A tests/tcg/mips/mips64-dspr2/subuh_r_qb.c
Log Message:
-----------
target-mips: Add ASE DSP testcases
Add MIPS ASE DSP testcases.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: b30706dda79894c01768df23cde526061d609258
https://github.com/qemu/qemu/commit/b30706dda79894c01768df23cde526061d609258
Author: Jia Liu <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/TODO
Log Message:
-----------
target-mips: Change TODO file
Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file.
Signed-off-by: Jia Liu <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 40e3acc18f1c663ee8f0c981525316f864f7b8ea
https://github.com/qemu/qemu/commit/40e3acc18f1c663ee8f0c981525316f864f7b8ea
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: remove #if defined(TARGET_MIPS64) in opcode enums
All switch() decoding instruction have a default entry, so it is possible
to have unused enum entries. Remove conditional definitions of MIPS64
opcode enums, as it only makes the code less readable.
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: ac4119c023c72b15f54238af43e4a178fcf41494
https://github.com/qemu/qemu/commit/ac4119c023c72b15f54238af43e4a178fcf41494
Author: Jan Kiszka <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M qemu-char.c
M qemu-char.h
M vl.c
Log Message:
-----------
chardev: Use timer instead of bottom-half to postpone open event
As the block layer may decide to flush bottom-halfs while the machine is
still initializing (e.g. to read geometry data from the disk), our
postponed open event may be processed before the last frontend
registered with a muxed chardev.
Until the semantics of BHs have been clarified, use an expired timer to
achieve the same effect (suggested by Paolo Bonzini). This requires to
perform the alarm timer initialization earlier as otherwise timer
subsystem can be used before being ready.
Signed-off-by: Jan Kiszka <address@hidden>
Commit: e1e1b25c97632cf68d6a11e20f8068282e3d7915
https://github.com/qemu/qemu/commit/e1e1b25c97632cf68d6a11e20f8068282e3d7915
Author: Richard Henderson <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-alpha/helper.h
Log Message:
-----------
target-alpha: Use TCG_CALL_NO_WG
Mark helper functions that raise exceptions, but otherwise do not
change TCG register state, with TCG_CALL_NO_WG.
Signed-off-by: Richard Henderson <address@hidden>
Commit: b3a1be87bac3a6aaa59bb88c1410f170dc9b22d5
https://github.com/qemu/qemu/commit/b3a1be87bac3a6aaa59bb88c1410f170dc9b22d5
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: don't remove op if output needs to be synced to memory
Commit 9c43b68de628a1e2cba556adfb71c17028eb802e do not correctly check
for dead outputs when they need to be synced to memory in case of
half-dead operations.
Fix that by applying the same pattern than for the default case.
Tested-by: Stefan Weil <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 4636401d99c113c67229ceabe93666767a619a25
https://github.com/qemu/qemu/commit/4636401d99c113c67229ceabe93666767a619a25
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: correctly restore btarget upon exception
When the CPU state is restored through retranslation after an exception,
btarget should also be restored.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 1e0e239a89b5a5ffe475a8efce5e59383a88af44
https://github.com/qemu/qemu/commit/1e0e239a89b5a5ffe475a8efce5e59383a88af44
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: do not save CPU state when using retranslation
When the CPU state after a possible retranslation is going to be handled
through code retranslation, we don't need to save the CPU state before.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: bbc1dedef6530917e34a94a2641932e636f9b02d
https://github.com/qemu/qemu/commit/bbc1dedef6530917e34a94a2641932e636f9b02d
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M fpu/softfloat-specialize.h
Log Message:
-----------
softfloat: implement fused multiply-add NaN propagation for MIPS
Add a pickNaNMulAdd function for MIPS, implementing NaN propagation
rules for MIPS fused multiply-add instructions.
Cc: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: b3d6cd447d594217cbfd09a3ffdf7b7893a1aa92
https://github.com/qemu/qemu/commit/b3d6cd447d594217cbfd09a3ffdf7b7893a1aa92
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/helper.h
M target-mips/op_helper.c
M target-mips/translate.c
Log Message:
-----------
target-mips: use the softfloat floatXX_muladd functions
Use the new softfloat floatXX_muladd() functions to implement the madd,
msub, nmadd and nmsub instructions. At the same time replace the name of
the helpers by the name of the instruction, as the only reason for the
previous names was to keep the macros simple.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 4a587b2ccb336e36817712ab21c513e35baa0eca
https://github.com/qemu/qemu/commit/4a587b2ccb336e36817712ab21c513e35baa0eca
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/op_helper.c
Log Message:
-----------
target-mips: keep softfloat exception set to 0 between instructions
Instead of clearing the softfloat exception flags before each floating
point instruction, reset them to 0 in update_fcr31() when an exception
is detected.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 5dbe90bba778c6ffcd0c7991ec67c4e7469e1c09
https://github.com/qemu/qemu/commit/5dbe90bba778c6ffcd0c7991ec67c4e7469e1c09
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/op_helper.c
Log Message:
-----------
target-mips: fix FPU exceptions
For each FPU instruction that can trigger an FPU exception, to call
call update_fcr31() after.
Remove the manual NaN assignment in case of float to float operation, as
softfloat is already taking care of that. However for float to int
operation, the value has to be changed to the MIPS one. In the cvtpw_ps
case, the two registers have to be handled separately to guarantee
a correct final value in both registers.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 4cc2e5f989728424e913777c494d68dbf0d2ec09
https://github.com/qemu/qemu/commit/4cc2e5f989728424e913777c494d68dbf0d2ec09
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/op_helper.c
Log Message:
-----------
target-mips: cleanup float to int conversion helpers
Instead of accessing the flags from the floating point control
register after updating it, read the softfloat flags.
This is just code cleanup and should not change the behaviour.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 05993cd05fcdebc75f8432cf6ad558726dc8ec15
https://github.com/qemu/qemu/commit/05993cd05fcdebc75f8432cf6ad558726dc8ec15
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/op_helper.c
Log Message:
-----------
target-mips: use softfloat constants when possible
softfloat already has a few constants defined, use them instead of
redefining them in target-mips.
Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and
FP_TO_INT64_OVERFLOW as even if they have the same value, they are
technically different (and defined differently in the MIPS ISA).
Remove the unused constants.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 5f7319cd84ecb82f65c67dd1033ec27647fcb7db
https://github.com/qemu/qemu/commit/5f7319cd84ecb82f65c67dd1033ec27647fcb7db
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/op_helper.c
Log Message:
-----------
target-mips: restore CPU state after an FPU exception
Rework *raise_exception*() functions so that they can be called from
other helpers, passing the return address as an argument.
Use do_raise_exception() function in update_fcr31() to correctly restore
the CPU state after an FPU exception.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 2910c6cbaacf7b9d54be3ce8ca03d68db45767bb
https://github.com/qemu/qemu/commit/2910c6cbaacf7b9d54be3ce8ca03d68db45767bb
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: cleanup load/store operations
Load/store operations use macros for historical reasons. Now that there
is no point in keeping them, replace them by direct calls to qemu_ld/st.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 3cee3050ce2d79837fa286a730a54e2a8b9dc5dc
https://github.com/qemu/qemu/commit/3cee3050ce2d79837fa286a730a54e2a8b9dc5dc
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: optimize load operations
Only allocate t1 when needed.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 18bba4dc781a273c2c1ff5baec2909c214e2e0fa
https://github.com/qemu/qemu/commit/18bba4dc781a273c2c1ff5baec2909c214e2e0fa
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/op_helper.c
Log Message:
-----------
target-mips: simplify load/store microMIPS helpers
load/store microMIPS helpers are reinventing the wheel. Call do_lw,
do_ll, do_sw and do_sl instead of using a macro calling the cpu_*
load/store functions.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: fc40787abcf8452b8f50d92b7a13243a12972c7a
https://github.com/qemu/qemu/commit/fc40787abcf8452b8f50d92b7a13243a12972c7a
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/helper.h
M target-mips/op_helper.c
M target-mips/translate.c
Log Message:
-----------
target-mips: implement unaligned loads using TCG
Load/store from helpers should be avoided as they are quite
inefficient. Rewrite unaligned loads instructions using TCG and
aligned loads. The number of actual loads operations to implement
an unaligned load instruction is reduced from up to 8 to 1.
Note: As we can't rely on shift by 32 or 64 undefined behaviour,
the code loads already shift by one constants.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 2d2826b99ee810057c76b48377d286beb9ee943b
https://github.com/qemu/qemu/commit/2d2826b99ee810057c76b48377d286beb9ee943b
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: don't use local temps for store conditional
Store conditional operations only need local temps in user mode. Fix
the code to use temp local only in user mode, this spares two memory
stores in system mode.
At the same time remove a wrong a wrong copied & pasted comment,
store operations don't have a register destination.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: acf124655873cf7256877a35efd8dacca1b199d8
https://github.com/qemu/qemu/commit/acf124655873cf7256877a35efd8dacca1b199d8
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: implement movn/movz using movcond
Avoid the branches in movn/movz implementation and replace them with
movcond. Also update a wrong command.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 51127181cfac0315720e6ca502eb133a353f6b11
https://github.com/qemu/qemu/commit/51127181cfac0315720e6ca502eb133a353f6b11
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: optimize ddiv/ddivu/div/divu with movcond
The result of a division by 0, or a division of INT_MIN by -1 in the
signed case, is unpredictable. Just replace 0 by 1 in that case so that
it doesn't trigger a floating point exception on the host.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: e0d002f17d1db1ade2b8d24b4a7c7ab361256726
https://github.com/qemu/qemu/commit/e0d002f17d1db1ade2b8d24b4a7c7ab361256726
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/translate.c
Log Message:
-----------
target-mips: use deposit instead of hardcoded version
Use the deposit op instead of and hardcoded bit field insertion. It
allows the host to emit the corresponding instruction if available.
At the same time remove the (lsb > msb) test. The MIPS64R2 instruction
set manual says "Because of the instruction format, lsb can never be
greater than msb, so there is no UNPREDICATABLE case for this
instruction."
(Bug reported as LP:1071149.)
Cc: Никита Канунников <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: bc3e45e13a93b883f0369acb2e19c0cec8705a7a
https://github.com/qemu/qemu/commit/bc3e45e13a93b883f0369acb2e19c0cec8705a7a
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/op_helper.c
Log Message:
-----------
target-mips: fix TLBR wrt SEGMask
Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask the
address.
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 286d52ebfc0d0d53c2a878e454292fea14bad41b
https://github.com/qemu/qemu/commit/286d52ebfc0d0d53c2a878e454292fea14bad41b
Author: Aurelien Jarno <address@hidden>
Date: 2012-10-31 (Wed, 31 Oct 2012)
Changed paths:
M target-mips/op_helper.c
Log Message:
-----------
target-mips: don't flush extra TLB on permissions upgrade
If the guest uses a TLBWI instruction for upgrading permissions, we
don't need to flush the extra TLBs. This improve boot time performance
by about 10%.
Signed-off-by: Aurelien Jarno <address@hidden>
Compare: https://github.com/qemu/qemu/compare/aee0bf7d8d75...286d52ebfc0d
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