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[Qemu-commits] [qemu/qemu] fcc803: target-xtensa: implement ATOMCTL SR

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] fcc803: target-xtensa: implement ATOMCTL SR
Date: Sat, 08 Dec 2012 12:30:08 -0800 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: fcc803d119a4c01a9b0ee5bda35fda1eeabffa33
      
https://github.com/qemu/qemu/commit/fcc803d119a4c01a9b0ee5bda35fda1eeabffa33
  Author: Max Filippov <address@hidden>
  Date:   2012-12-08 (Sat, 08 Dec 2012)

  Changed paths:
    M target-xtensa/cpu.c
    M target-xtensa/cpu.h
    M target-xtensa/helper.c
    M target-xtensa/helper.h
    M target-xtensa/op_helper.c
    M target-xtensa/overlay_tool.h
    M target-xtensa/translate.c

  Log Message:
  -----------
  target-xtensa: implement ATOMCTL SR

ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory
type. See ISA, 4.3.12.4 for details.

Signed-off-by: Max Filippov <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>


  Commit: 4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770
      
https://github.com/qemu/qemu/commit/4e41d2f5830a76d3fe92b3d3b18cc9f2ee927770
  Author: Max Filippov <address@hidden>
  Date:   2012-12-08 (Sat, 08 Dec 2012)

  Changed paths:
    M target-xtensa/cpu.c
    M target-xtensa/cpu.h
    M target-xtensa/helper.c
    M target-xtensa/overlay_tool.h
    M target-xtensa/translate.c

  Log Message:
  -----------
  target-xtensa: implement CACHEATTR SR

In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details.

Signed-off-by: Max Filippov <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>


  Commit: fe0bd475aa31e60674f7f53b85dc293108026202
      
https://github.com/qemu/qemu/commit/fe0bd475aa31e60674f7f53b85dc293108026202
  Author: Max Filippov <address@hidden>
  Date:   2012-12-08 (Sat, 08 Dec 2012)

  Changed paths:
    M target-xtensa/cpu.h
    M target-xtensa/overlay_tool.h
    M target-xtensa/translate.c

  Log Message:
  -----------
  target-xtensa: restrict available SRs by enabled options

Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr,
xsr) are associated with their corresponding SR and raise illegal opcode
exception in case the register is not configured for the core.

Signed-off-by: Max Filippov <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>


  Commit: 53593e90d13264dc88b3281ddf75ceaa641df05a
      
https://github.com/qemu/qemu/commit/53593e90d13264dc88b3281ddf75ceaa641df05a
  Author: Max Filippov <address@hidden>
  Date:   2012-12-08 (Sat, 08 Dec 2012)

  Changed paths:
    M target-xtensa/translate.c

  Log Message:
  -----------
  target-xtensa: better control rsr/wsr/xsr access to SRs

There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs,
and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal
opcode exception on illegal access to these SRs.

Signed-off-by: Max Filippov <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>


  Commit: b7909d81f7658f64bba0faed83e7c2fd6a52fcba
      
https://github.com/qemu/qemu/commit/b7909d81f7658f64bba0faed83e7c2fd6a52fcba
  Author: Max Filippov <address@hidden>
  Date:   2012-12-08 (Sat, 08 Dec 2012)

  Changed paths:
    M target-xtensa/cpu.h
    M target-xtensa/overlay_tool.h
    M target-xtensa/translate.c

  Log Message:
  -----------
  target-xtensa: implement MISC SR

The Miscellaneous Special Registers Option provides zero to four scratch
registers within the processor readable and writable by RSR, WSR, and
XSR. These registers are privileged. They may be useful for some
application-specific exception and interrupt processing tasks in the
kernel. The MISC registers are undefined after reset.
See ISA, 4.7.3 for details.

Signed-off-by: Max Filippov <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>


  Commit: efdfac94f48f8589a0d60b650c7bed989a341eaa
      
https://github.com/qemu/qemu/commit/efdfac94f48f8589a0d60b650c7bed989a341eaa
  Author: Max Filippov <address@hidden>
  Date:   2012-12-08 (Sat, 08 Dec 2012)

  Changed paths:
    M tests/tcg/xtensa/Makefile
    M tests/tcg/xtensa/macros.inc
    A tests/tcg/xtensa/test_sr.S

  Log Message:
  -----------
  target-xtensa: add SR accessibility unit tests

Signed-off-by: Max Filippov <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>


  Commit: 5dacd229ebb46c236cb1dd0c65a4e4f2cfb55dfb
      
https://github.com/qemu/qemu/commit/5dacd229ebb46c236cb1dd0c65a4e4f2cfb55dfb
  Author: Max Filippov <address@hidden>
  Date:   2012-12-08 (Sat, 08 Dec 2012)

  Changed paths:
    M tests/tcg/xtensa/Makefile
    A tests/tcg/xtensa/test_s32c1i.S

  Log Message:
  -----------
  target-xtensa: add s32c1i unit tests

Signed-off-by: Max Filippov <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>


  Commit: f877d09e63bd94424dab049da75bc1cd601a7609
      
https://github.com/qemu/qemu/commit/f877d09e63bd94424dab049da75bc1cd601a7609
  Author: Max Filippov <address@hidden>
  Date:   2012-12-08 (Sat, 08 Dec 2012)

  Changed paths:
    M target-xtensa/translate.c

  Log Message:
  -----------
  target-xtensa: use movcond where possible

Use movcond for all sorts of conditional moves, ABS, CLAMPS, MIN/MAX
opcodes.

Signed-off-by: Max Filippov <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>


  Commit: 24c35a504e8b09e697d0268bbefb2a329b901611
      
https://github.com/qemu/qemu/commit/24c35a504e8b09e697d0268bbefb2a329b901611
  Author: Peter Maydell <address@hidden>
  Date:   2012-12-08 (Sat, 08 Dec 2012)

  Changed paths:
    M linux-user/arm/syscall_nr.h
    M linux-user/i386/syscall_nr.h
    M linux-user/sparc/syscall_nr.h
    M linux-user/strace.list
    M linux-user/syscall.c
    M linux-user/unicore32/syscall_nr.h

  Log Message:
  -----------
  linux-user: Merge pread/pwrite into pread64/pwrite64

The Linux syscalls underlying pread() and pwrite() take a 64 bit
offset on all architectures, even if some of them name the syscall
"pread/pwrite" rather than "pread64/pwrite64" for historical reasons.
So move the four QEMU target architectures (arm, i386, sparc,
unicore32) which were defining TARGET_NR_pread/pwrite to define
TARGET_NR_pread64/pwrite64 instead, and drop the TARGET_NR_pread/pwrite
implementation code completely.

(Based on examination of the kernel sources for the four architectures
this patch affects.)

Signed-off-by: Peter Maydell <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>


  Commit: e49d021e574c3ee8e443bcc84d1fb7dfb4c87c42
      
https://github.com/qemu/qemu/commit/e49d021e574c3ee8e443bcc84d1fb7dfb4c87c42
  Author: Peter Maydell <address@hidden>
  Date:   2012-12-08 (Sat, 08 Dec 2012)

  Changed paths:
    M configure

  Log Message:
  -----------
  configure: Default to 'cc', not 'gcc'

Default to 'cc' as our compiler, rather than 'gcc'. We used to have
to insist on gcc when we still kept the CPU env in a fixed global
register, but this is no longer necessary and we will now compile OK
on clang as well as gcc.  Using 'cc' should generally result in us
using the most standard and maintained system compiler for the
platform.  (For instance on newer MacOS X 'gcc' exists but is an
elderly compiler provided mostly for legacy reasons, and 'cc'
(which is clang) is definitely the better choice.) On Linux there
will generally be no user-visible change since cc will be gcc.

This changeover necessitates a slight reworking of how we set the
'cc' variable, because GNU cross toolchains generally provide a
'${cross_prefix}gcc' but not a '${cross_prefix}cc'.

Signed-off-by: Peter Maydell <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>


Compare: https://github.com/qemu/qemu/compare/536b558f5896...e49d021e574c
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