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[Qemu-commits] [qemu/qemu] 0ba365: target-mips: fix EXTPDP and setting u


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 0ba365: target-mips: fix EXTPDP and setting up pos field i...
Date: Sun, 19 May 2013 07:00:09 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0ba365f4a9752a82502e829a3e8cb5f03a1ffc0c
      
https://github.com/qemu/qemu/commit/0ba365f4a9752a82502e829a3e8cb5f03a1ffc0c
  Author: Petar Jovanovic <address@hidden>
  Date:   2013-05-19 (Sun, 19 May 2013)

  Changed paths:
    M target-mips/dsp_helper.c
    M tests/tcg/mips/mips32-dsp/extpdp.c

  Log Message:
  -----------
  target-mips: fix EXTPDP and setting up pos field in the DSPControl reg

This change makes sure that modifications of pos field in the DSPControl
register do not trash other bits in the register. This bug can be triggered
with the additional test case in mips32-dsp/extpdp.c in this commit.

In addition to this, this change corrects incorrect calculation of the mask
for EXTPDP.

Signed-off-by: Petar Jovanovic <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 118d1e4f59c36078a0d76d090d4c16deace47233
      
https://github.com/qemu/qemu/commit/118d1e4f59c36078a0d76d090d4c16deace47233
  Author: Petar Jovanovic <address@hidden>
  Date:   2013-05-19 (Sun, 19 May 2013)

  Changed paths:
    M target-mips/dsp_helper.c

  Log Message:
  -----------
  target-mips: set carry bit correctly in DSPControl register

First we need to clear the bit and then we set the given value.
Instruction ADDSC sets the bit and instruction ADDWC uses this bit.

Signed-off-by: Petar Jovanovic <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


Compare: https://github.com/qemu/qemu/compare/489ed4bbae30...118d1e4f59c3

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