[Qemu-commits] [qemu/qemu] ccd380: target-arm: Split out private-to-target functions ...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ccd380876b79c3b46f85720c1be8e2cd40509460
      
https://github.com/qemu/qemu/commit/ccd380876b79c3b46f85720c1be8e2cd40509460
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    A target-arm/internals.h
    M target-arm/kvm32.c
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Split out private-to-target functions into internals.h

Currently cpu.h defines a mixture of functions and types needed by
the rest of QEMU and those needed only by files within target-arm/.
Split the latter out into a new header so they aren't needlessly
exposed further than required.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: c2b820fe587b18448967cdd6d408abd1dc0471f2
      
https://github.com/qemu/qemu/commit/c2b820fe587b18448967cdd6d408abd1dc0471f2
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 DAIF system register

Implement the DAIF system register which is a view of the
DAIF bits in PSTATE. To avoid needing a readfn, we widen
the daif field in CPUARMState to uint64_t.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: abf1172fc6dbc9564e25039434d444d9a9f1e88a
      
https://github.com/qemu/qemu/commit/abf1172fc6dbc9564e25039434d444d9a9f1e88a
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M linux-user/main.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: Define exception record for AArch64 exceptions

For AArch32 exceptions, the only information provided about
the cause of an exception is the individual exception type (data
abort, undef, etc), which we store in cs->exception_index. For
AArch64, the CPU provides much more detail about the cause of
the exception, which can be found in the syndrome register.
Create a set of fields in CPUARMState which must be filled in
whenever an exception is raised, so that exception entry can
correctly fill in the syndrome register for the guest.
This includes the information which in AArch32 appears in
the DFAR and IFAR (fault address registers) and the DFSR
and IFSR (fault status registers) for data aborts and
prefetch aborts, since if we end up taking the MMU fault
to AArch64 rather than AArch32 this will need to end up
in different system registers.

This patch does a refactoring which moves the setting of the
AArch32 DFAR/DFSR/IFAR/IFSR from the point where the exception
is raised to the point where it is taken. (This is no change
for cores with an MMU, retains the existing clearly incorrect
behaviour for ARM946 of trashing the MP access permissions
registers which share the c5_data and c5_insn state fields,
and has no effect for v7M because we don't implement its
MPU fault status or address registers.)

As a side effect of the cleanup we fix a bug in the AArch64
linux-user mode code where we were passing a 64 bit fault
address through the 32 bit c6_data/c6_insn fields: it now
goes via the always-64-bit exception.vaddress.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 8bcbf37caa87ba89bc391bad70039f942a98c7e3
      
https://github.com/qemu/qemu/commit/8bcbf37caa87ba89bc391bad70039f942a98c7e3
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.h
    M target-arm/internals.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Provide correct syndrome information for cpreg access traps

For exceptions taken to AArch64, if a coprocessor/system register
access fails due to a trap or enable bit then the syndrome information
must include details of the failing instruction (crn/crm/opc1/opc2
fields, etc). Make the decoder construct the syndrome information
at translate time so it can be passed at runtime to the access-check
helper function and used as required.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: d4a2dc675bde36443c3a73051ca863d878d8bc31
      
https://github.com/qemu/qemu/commit/d4a2dc675bde36443c3a73051ca863d878d8bc31
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.h
    M target-arm/internals.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Add support for generating exceptions with syndrome information

Add new helpers exception_with_syndrome (for generating an exception
with syndrome information) and exception_uncategorized (for generating
an exception with "Unknown or Uncategorized Reason", which have a syndrome
register value of zero), and use them to generate the correct syndrome
information for exceptions which are raised directly from generated code.

This patch includes moving the A32/T32 gen_exception_insn functions
further up in the source file; they will be needed for "VFP/Neon disabled"
exception generation later.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 00892383c9f5f663230921c6cf6b6d3a8a61b45b
      
https://github.com/qemu/qemu/commit/00892383c9f5f663230921c6cf6b6d3a8a61b45b
  Author: Rob Herring <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.c
    M target-arm/internals.h

  Log Message:
  -----------
  target-arm: Provide syndrome information for MMU faults

Set up the required syndrome information when we detect an MMU fault.

Signed-off-by: Rob Herring <address@hidden>
[PMM: split out from exception handling patch, tweaked to bring
 in line with how we create other kinds of syndrome information]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 8c6afa6ab158467d1938cc92022135bc7a872006
      
https://github.com/qemu/qemu/commit/8c6afa6ab158467d1938cc92022135bc7a872006
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/internals.h
    M target-arm/translate-a64.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set

For the A64 instruction set, the only FP/Neon disable trap
is the CPACR FPEN bits, which may indicate "enabled", "disabled"
or "disabled for EL0". Add a bit to the AArch64 tb flags indicating
whether FP/Neon access is currently enabled and make the decoder
emit code to raise exceptions on use of FP/Neon insns if it is not.

We use a new flag in DisasContext rather than borrowing the
existing vfp_enabled flag because the A32/T32 decoder is going
to need both.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Peter Crosthwaite <address@hidden>
---
I'm aware this is a rather hard to review patch; sorry.
I have done an exhaustive check that we have fp access checks
in all code paths with the aid of the assertions added in the
next patch plus the code-coverage hack patch I posted to the
list earlier.

This patch is correct as of
09e037354 target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)
which was the last of the Neon insns to be added, so assuming
no refactoring of the code it should be fine.


  Commit: 90e496386fe7fd32c189561f846b7913f95b8cf4
      
https://github.com/qemu/qemu/commit/90e496386fe7fd32c189561f846b7913f95b8cf4
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/translate-a64.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: A64: Add assertion that FP access was checked

Because unallocated encodings generate different exception syndrome
information from traps due to FP being disabled, we can't do a single
"is fp access disabled" check at a high level in the decode tree.
To help in catching bugs where the access check was forgotten in some
code path, we set this flag when the access check is done, and assert
that it is set at the point where we actually touch the FP regs.

This requires us to pass the DisasContext to the vec_reg_offset
and fp_reg_offset functions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 2c7ffc414d8591018248b5487757e45f7bb6bd3c
      
https://github.com/qemu/qemu/commit/2c7ffc414d8591018248b5487757e45f7bb6bd3c
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1

The current A32/T32 decoder bases its "is VFP/Neon enabled?" check
on the FPSCR.EN bit. This is correct if EL1 is AArch32, but for
an AArch64 EL1 the logic is different: it must act as if FPSCR.EN
is always set. Instead, trapping must happen according to CPACR
bits for cp10/cp11; these cover all of FP/Neon, including the
FPSCR/FPSID/MVFR register accesses which FPSCR.EN does not affect.
Add support for CPACR checks (which are also required for ARMv7,
but were unimplemented because Linux happens not to use them)
and make sure they generate exceptions with the correct syndrome.

We actually return incorrect syndrome information for cases
where FP is disabled but the specific instruction bit pattern
is unallocated: strictly these should be the Uncategorized
exception, not a "SIMD disabled" exception. This should be
mostly harmless, and the structure of the A32/T32 VFP/Neon
decoder makes it painful to put the 'FP disabled?' checks in
the right places.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 2c8dd318639a37c308d7946d9f6548727dfc32ca
      
https://github.com/qemu/qemu/commit/2c8dd318639a37c308d7946d9f6548727dfc32ca
  Author: Rob Herring <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add v8 mmu translation support

Add support for v8 page table walks. This supports stage 1 translations
for 4KB, 16KB and 64KB page sizes starting with 0 or 1 level.

Signed-off-by: Rob Herring <address@hidden>
[PMM: fix style nits, fold in 16/64K page support patch, use
 arm_el_is_aa64() to decide whether to do 64 bit page table walk]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 9225d739e7f6ec8d2139f79c3d2e3282cc725364
      
https://github.com/qemu/qemu/commit/9225d739e7f6ec8d2139f79c3d2e3282cc725364
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Don't mention PMU in debug feature register

Suppress the ID_AA64DFR0_EL1 PMUVer field, even if the CPU specific
value claims that it exists. QEMU doesn't currently implement it,
and not advertising it prevents the guest from trying to use it
and getting UNDEFs on unimplemented registers.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
This is arguably a hack, but otherwise Linux tries to prod
half a dozen PMU sysregs.


  Commit: aca3f40b374428e9c01068cf96294483cbb760a0
      
https://github.com/qemu/qemu/commit/aca3f40b374428e9c01068cf96294483cbb760a0
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M include/exec/softmmu_exec.h
    M target-arm/cpu-qom.h
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement DC ZVA

Implement the DC ZVA instruction, which clears a block of memory.
The fast path obtains a pointer to the underlying RAM via the TCG TLB
data structure so we can do a direct memset(), with fallback to a
simple byte-store loop in the slow path.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Acked-by: Peter Crosthwaite <address@hidden>


  Commit: 7e09797c299712cafa7bc05dd57c1b13afcc6039
      
https://github.com/qemu/qemu/commit/7e09797c299712cafa7bc05dd57c1b13afcc6039
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Use dedicated CPU state fields for ARM946 access bit registers

The ARM946 model currently uses the c5_data and c5_insn fields in the CPU
state struct to store the contents of its access permission registers.
This is confusing and a good source of bugs because for all the MMU-based
CPUs those fields are fault status and fault address registers, which
behave completely differently; they just happen to use the same cpreg
encoding. Split them out to use their own fields instead.

These registers are only present in PMSAv5 MPU systems (of which the
ARM946 is our only current example); PMSAv6 and PMSAv7 (which we have
no implementations of) handle access permissions differently. We name
the new state fields accordingly.

Note that this change fixes a bug where a data abort or prefetch abort
on the ARM946 would accidentally corrupt the access permission registers
because the interrupt handling code assumed the c5_data and c5_insn
fields were always fault status registers.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 6cd8a2649aafb8e53db4a8f0bf0ea629441f8c03
      
https://github.com/qemu/qemu/commit/6cd8a2649aafb8e53db4a8f0bf0ea629441f8c03
  Author: Rob Herring <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 views of fault status and data registers

Implement AArch64 views of ESR_EL1 and FAR_EL1, and make the 32 bit
DFSR, DFAR, IFAR share state with them as architecturally specified.
The IFSR doesn't share state with any AArch64 register visible at EL1,
so just rename the state field without widening it to 64 bits.

Signed-off-by: Rob Herring <address@hidden>
[PMM: Minor tweaks; fix some bugs involving inconsistencies between
 use of offsetof() or offsetoflow32() and struct field width]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: a0618a1990e4df30a76cf5b441b4aa7f002b0d64
      
https://github.com/qemu/qemu/commit/a0618a1990e4df30a76cf5b441b4aa7f002b0d64
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/kvm64.c
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: Add AArch64 ELR_EL1 register.

Add the AArch64 ELR_EL1 register.

Note that this does not live in env->cp15: for KVM migration
compatibility we need to migrate it separately rather than
as part of the system registers, because the KVM-to-userspace
interface puts it in the struct kvm_regs rather than making
them visible via the ONE_REG ioctls.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: f502cfc207ff288ec1f3dac10024c51ffe64a65d
      
https://github.com/qemu/qemu/commit/f502cfc207ff288ec1f3dac10024c51ffe64a65d
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/kvm64.c
    M target-arm/machine.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Implement SP_EL0, SP_EL1

Implement handling for the AArch64 SP_EL0 system register.
This holds the EL0 stack pointer, and is only accessible when
it's not being used as the stack pointer, ie when we're in EL1
and EL1 is using its own stack pointer. We also provide a
definition of the SP_EL1 register; this isn't guest visible
as a system register for an implementation like QEMU which
doesn't provide EL2 or EL3; however it is useful for ensuring
the underlying state is migrated.

We need to update the state fields in the CPU state whenever
we switch stack pointers; this happens when we take an exception
and also when SPSEL is used to change the bit in PSTATE which
indicates which stack pointer EL1 should use.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: a65f1de982302f5c33f668ad25a120eba7993d37
      
https://github.com/qemu/qemu/commit/a65f1de982302f5c33f668ad25a120eba7993d37
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: Implement AArch64 SPSR_EL1

Implement the AArch64 SPSR_EL1. For compatibility with how KVM
handles SPSRs and with the architectural mapping between AArch32
and AArch64, we put this in the banked_spsr[] array in the slot
that is used for SVC in AArch32. This means we need to extend the
array from uint32_t to uint64_t, which requires some reworking
of the 32 bit KVM save/restore code.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Peter Crosthwaite <address@hidden>


  Commit: 2f2a00aec9838bc52ac4f5dd452f4cf533effa88
      
https://github.com/qemu/qemu/commit/2f2a00aec9838bc52ac4f5dd452f4cf533effa88
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.c
    M target-arm/internals.h

  Log Message:
  -----------
  target-arm: Move arm_log_exception() into internals.h

Move arm_log_exception() into internals.h so we can use it from
helper-a64.c for the AArch64 exception entry code.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 52e60cdd342dc48116edb81b443ba8c0a0c6f1a3
      
https://github.com/qemu/qemu/commit/52e60cdd342dc48116edb81b443ba8c0a0c6f1a3
  Author: Rob Herring <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu64.c
    M target-arm/helper-a64.c
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Implement AArch64 EL1 exception handling

Implement exception handling for AArch64 EL1. Exceptions from AArch64 or
AArch32 EL0 are supported.

Signed-off-by: Rob Herring <address@hidden>
[PMM: fixed minor style nits; updated to match changes in
 previous patches; added some of the simpler cases of
 illegal-exception-return support]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: a50c0f51339ed1df0a2e289513e3e2bf5b5ca45c
      
https://github.com/qemu/qemu/commit/a50c0f51339ed1df0a2e289513e3e2bf5b5ca45c
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Implement ARMv8 MVFR registers

For ARMv8 there are two changes to the MVFR media feature registers:
 * there is a new MVFR2 which is accessible from 32 bit code
 * 64 bit code accesses these via the usual sysreg instructions
   rather than with a floating-point specific instruction

Implement this.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: cb1fa941c121d76dc17cecb794cf18dabd38d014
      
https://github.com/qemu/qemu/commit/cb1fa941c121d76dc17cecb794cf18dabd38d014
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: Add Cortex-A57 processor

Add Cortex-A57 processor.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Peter Crosthwaite <address@hidden>


  Commit: 0ff644a786aa041a8616ce449382806d8e29d04c
      
https://github.com/qemu/qemu/commit/0ff644a786aa041a8616ce449382806d8e29d04c
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 views of AArch32 ID registers

All the AArch32 ID registers are visible from AArch64
(in addition to the AArch64-specific ID_AA64* registers).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 014406b510faae91b801c8c6fd408a7609f6de0b
      
https://github.com/qemu/qemu/commit/014406b510faae91b801c8c6fd408a7609f6de0b
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 view of CONTEXTIDR

Implement AArch64 view of the CONTEXTIDR register.
We tighten up the condition when we flush the TLB on a CONTEXTIDR
write to avoid needlessly flushing the TLB every time on a 64
bit system (and also on a 32 bit system using LPAE, as a bonus).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 2eef0bf82146034f756d39cb02c8c8dd561a8942
      
https://github.com/qemu/qemu/commit/2eef0bf82146034f756d39cb02c8c8dd561a8942
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 view of ACTLR

Implement the AArch64 view of the ACTLR (auxiliary control
register). Note that QEMU internally tends to call this
AUXCR for historical reasons.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 1090b9c6ccfe837f1c76dafb7e56031bd7844075
      
https://github.com/qemu/qemu/commit/1090b9c6ccfe837f1c76dafb7e56031bd7844075
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement ISR_EL1 register

Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 85acfa9c38880d5d2b3cc71a5e541a267c9f7396
      
https://github.com/qemu/qemu/commit/85acfa9c38880d5d2b3cc71a5e541a267c9f7396
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: Remove THUMB2EE feature from AArch64 'any' CPU

The AArch64 usermode 'any' CPU type was accidentally specified
with the ARM_FEATURE_THUMB2EE bit set. This is incorrect since
ARMv8 removes Thumb2EE completely. Since we never implemented
Thumb2EE anyway having the feature bit set was fairly harmless
for user-mode, but the correct thing is to not set it at all.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 00a29f3ddcd506f2fdba4d115e6c8df676f203db
      
https://github.com/qemu/qemu/commit/00a29f3ddcd506f2fdba4d115e6c8df676f203db
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Don't expose wildcard ID register definitions for ARMv8

In ARMv8 the 32 bit coprocessor ID register space is tidied up to
remove the wildcarded aliases of the MIDR and the RAZ behaviour
for the unassigned space where crm = 3..7. Make sure we don't
expose thes wildcards for v8 cores. This means we need to have
a specific implementation for REVIDR, an IMPDEF register which
may be the same as the MIDR (and which we always implement as such).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 9449fdf61fc32e50e29d9bc5b531f1d238c13c97
      
https://github.com/qemu/qemu/commit/9449fdf61fc32e50e29d9bc5b531f1d238c13c97
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8

Many of the reginfo definitions in cp_reginfo[] use CP_ANY wildcards.
This is for a combination of reasons:
 * early ARM implementations really did underdecode
 * earlier versions of QEMU underdecoded and we can't tighten
   this up because we don't know if guests really require this or not
 * implementation convenience

For ARMv8 the architecture has tightened things up and system and
coprocessor registers are always specifically decoded. We take
advantage of this opportunity for a clean break by restricting
our CP_ANY wildcarded reginfo to pre-v8 CPUs, and providing
specifically decoded versions where necessary for v8 CPUs.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Peter Crosthwaite <address@hidden>


  Commit: f32cdad55de242a23aae9842cdb659e6de116352
      
https://github.com/qemu/qemu/commit/f32cdad55de242a23aae9842cdb659e6de116352
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement auxiliary fault status registers

Implement the auxiliary fault status registers AFSR0_EL1 and
AFSR1_EL1. These are present on v7 and later, and have IMPDEF
behaviour; we choose to RAZ/WI for all cores.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 19525524a755a98f72b80c92c4f6bdeea3002da5
      
https://github.com/qemu/qemu/commit/19525524a755a98f72b80c92c4f6bdeea3002da5
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 address translation operations

Implement the AArch64 address translation operations.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 3933443e38f37576d63247a846ca342da53e7d43
      
https://github.com/qemu/qemu/commit/3933443e38f37576d63247a846ca342da53e7d43
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement RVBAR register

Implement the AArch64 RVBAR register, which indicates the reset
address. Since the reset address is implementation defined and
usually configurable by setting config signals in hardware, we
also provide a QOM property so it can be set at board level if
necessary.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 377a44ec8f2fac5b7bef41d212dfbabf53c8c810
      
https://github.com/qemu/qemu/commit/377a44ec8f2fac5b7bef41d212dfbabf53c8c810
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: Implement Cortex-A57 implementation-defined system registers

Implement a subset of the Cortex-A57's implementation defined system
registers. We provide RAZ/WI or reads-as-constant/writes-ignored
implementations of the various control and syndrome reigsters.
We do not implement registers which provide direct access to and
manipulation of the L1 cache, since QEMU doesn't implement caches.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Peter Crosthwaite <address@hidden>


  Commit: f318cec6adcb73c688d68b0874686a30c0f34a2e
      
https://github.com/qemu/qemu/commit/f318cec6adcb73c688d68b0874686a30c0f34a2e
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement CBAR for Cortex-A57

The Cortex-A57, like most of the other ARM cores, has a CBAR
register which defines the base address of the per-CPU
peripherals. However it has a 64-bit view as well as a
32-bit view; expand the QOM reset-cbar property from UINT32
to UINT64 so this can be specified, and implement the
32-bit and 64-bit views of a 64-bit CBAR.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: c29f9a0a29e76b36fd1bb6f5adf7841c6fdbc0b3
      
https://github.com/qemu/qemu/commit/c29f9a0a29e76b36fd1bb6f5adf7841c6fdbc0b3
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  target-arm: Make Cortex-A15 CBAR read-only

The Cortex-A15's CBAR register is actually read-only (unlike that
of the Cortex-A9). Correct our model to match the hardware.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 7633378d5fbe932c9d38ae8961ef035d1ed26bfd
      
https://github.com/qemu/qemu/commit/7633378d5fbe932c9d38ae8961ef035d1ed26bfd
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc

The AArch64 implementation of the set_pc method needs to be updated to
handle the possibility that the CPU is in AArch32 mode; otherwise there
are weird crashes when doing interprocessing in system emulation mode
when an interrupt occurs and we fail to resynchronize the 32-bit PC
with the TB we need to execute next.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 177311157c9dbd408728620771b1fceb65d26846
      
https://github.com/qemu/qemu/commit/177311157c9dbd408728620771b1fceb65d26846
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32

For system mode, we may have a 64 bit CPU which is currently executing
in AArch32 state; if we're dumping CPU state to the logs we should
therefore show the correct state for the current execution state,
rather than hardwiring it based on the type of the CPU. For consistency
with how we handle translation, we leave the 32 bit dump function
as the default, and have it hand off control to the 64 bit dump code
if we're in AArch64 mode.

Reported-by: Rob Herring <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b5cde1da0a67aa9841da46ca804b48098e63e838
      
https://github.com/qemu/qemu/commit/b5cde1da0a67aa9841da46ca804b48098e63e838
  Author: Chen Gang <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/gdbstub64.c

  Log Message:
  -----------
  target-arm/gdbstub64.c: remove useless 'break' statement.

Clean up useless 'break' statement after 'return' statement.

Signed-off-by: Chen Gang <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f727d0e6219e6d5a9f91326f01b85aa563e37bb9
      
https://github.com/qemu/qemu/commit/f727d0e6219e6d5a9f91326f01b85aa563e37bb9
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/timer/cadence_ttc.c

  Log Message:
  -----------
  timer: cadence_ttc: Fix match register write logic

This switch logic should not fall through. Fix.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1c70aa6264ea7f3d7be6f3acb65a1e0aac8b3944
      
https://github.com/qemu/qemu/commit/1c70aa6264ea7f3d7be6f3acb65a1e0aac8b3944
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/intc/allwinner-a10-pic.c

  Log Message:
  -----------
  allwinner-a10-pic: set vector address when an interrupt is pending

This patch implements proper updating of the vector register which
should hold, according to the A10 user manual, the vector address for
the interrupt currently active on the CPU IRQ input.

Interrupt priority is not implemented at the moment and thus the first
pending interrupt is returned.

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Li Guang <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2237094d9619a64b669ca9f7fb1430b9b329f9cf
      
https://github.com/qemu/qemu/commit/2237094d9619a64b669ca9f7fb1430b9b329f9cf
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/intc/allwinner-a10-pic.c

  Log Message:
  -----------
  allwinner-a10-pic: fix behaviour of pending register

The pending register is read-only and the value returned upon a read
reflects the state of irq input pins (interrupts are level triggered).
This patch implements such behaviour.

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Li Guang <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 323a8771cfb96ab752c9d27e939a2fbac1380b1c
      
https://github.com/qemu/qemu/commit/323a8771cfb96ab752c9d27e939a2fbac1380b1c
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/timer/allwinner-a10-pit.c
    M include/hw/timer/allwinner-a10-pit.h

  Log Message:
  -----------
  allwinner-a10-pit: avoid generation of spurious interrupts

The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing explicitly the timer
index to the callback function.

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Li Guang <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
[PMM: avoid duplicate typedef of AwA10PITState]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a63f9f85e387791e7a94480379ca5421a0b6d580
      
https://github.com/qemu/qemu/commit/a63f9f85e387791e7a94480379ca5421a0b6d580
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/timer/allwinner-a10-pit.c

  Log Message:
  -----------
  allwinner-a10-pit: use level triggered interrupts

Convert the interrupt generation logic to the use of level triggered
interrupts.

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 286226a47980d25f95afe920d430d3bbcb883546
      
https://github.com/qemu/qemu/commit/286226a47980d25f95afe920d430d3bbcb883546
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/arm/cubieboard.c
    M hw/timer/allwinner-a10-pit.c
    M include/hw/timer/allwinner-a10-pit.h

  Log Message:
  -----------
  allwinner-a10-pit: implement prescaler and source selection

This implements the prescaler and source fields of the timer control
register. The source for each timer can be selected among 4 clock
inputs whose frequencies are set through model properties.

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 103db49a106d1f015a16432eb73cc4046792fbad
      
https://github.com/qemu/qemu/commit/103db49a106d1f015a16432eb73cc4046792fbad
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/net/allwinner_emac.c
    M include/hw/net/allwinner_emac.h

  Log Message:
  -----------
  allwinner-emac: set autonegotiation complete bit on link up

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6619bc5c55c1322a89009e2edd530113da95d551
      
https://github.com/qemu/qemu/commit/6619bc5c55c1322a89009e2edd530113da95d551
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/net/allwinner_emac.c

  Log Message:
  -----------
  allwinner-emac: update irq status after writes to interrupt registers

The irq line status must be updated after writes to the INT_CTL and
INT_STA registers.

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: db302f8f9364580a90b383d8531d28500e4e5bb5
      
https://github.com/qemu/qemu/commit/db302f8f9364580a90b383d8531d28500e4e5bb5
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/misc/zynq_slcr.c

  Log Message:
  -----------
  misc: zynq-slcr: Rewrite

Near total rewrite of this device model. It is stylistically
obsolete, has numerous coverity fails and is not up to date with latest
Xilinx documentation. Fix.

The registers are flattened into a single array. This greatly simplifies
the MMIO accessor functions.

We take the oppurtunity to update the register Macro definitions to
match the latest TRM. Xilinx has de-documented some regs hence there are
some straight deletions. We only do this however in the case or a stock
read-as-written reset-zero register. Non-zero resets are always
preserved. New register definitions are added as needed.

This all comes with a VMSD version break as the union layout from before
was a bit strange and we are better off without it.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 15e3611e1ca7a3b4d2cee505df83ea2744c2874d
      
https://github.com/qemu/qemu/commit/15e3611e1ca7a3b4d2cee505df83ea2744c2874d
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/misc/zynq_slcr.c

  Log Message:
  -----------
  misc: zynq_slcr: Convert SBD::init to object init

To bring it up to date with styling guidelines.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6954a1cd97f7669b320967d11833fe0d6d7a742d
      
https://github.com/qemu/qemu/commit/6954a1cd97f7669b320967d11833fe0d6d7a742d
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/misc/zynq_slcr.c

  Log Message:
  -----------
  misc: zynq_slcr: Make DB_PRINTs always compile

Change the DB_PRINT macro over to a regular if() rather than
conditional compilation to give constant compile testing of formats.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 553893736885e4f2dda424bff3e2200e1b6482a5
      
https://github.com/qemu/qemu/commit/553893736885e4f2dda424bff3e2200e1b6482a5
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  net: cadence_gem: Make phy respond to broadcast

Phys must respond to address 0 by specification. Implement.

Signed-off-by: Nathan Rossi <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Beniamino Galvani <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 33bbd75a7c3321432fe40a8cbacd64619c56138c
      
https://github.com/qemu/qemu/commit/33bbd75a7c3321432fe40a8cbacd64619c56138c
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  arm: translate.c: Fix smlald Instruction

The smlald (and probably smlsld) instruction was doing incorrect sign
extensions of the operands amongst 64bit result calculation. The
instruction psuedo-code is:

 operand2 = if m_swap then ROR(R[m],16) else R[m];
 product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
 product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
 result = product1 + product2 + SInt(R[dHi]:R[dLo]);
 R[dHi] = result<63:32>;
 R[dLo] = result<31:0>;

The result calculation should be done in 64 bit arithmetic, and hence
product1 and product2 should be sign extended to 64b before calculation.

The current implementation was adding product1 and product2 together
then sign-extending the intermediate result leading to false negatives.

E.G. if product1 = product2 = 0x4000000, their sum = 0x80000000, which
will be incorrectly interpreted as -ve on sign extension.

We fix by doing the 64b extensions on both product1 and product2 before
any addition/subtraction happens.

We also fix where we were possibly incorrectly setting the Q saturation
flag for SMLSLD, which the ARM ARM specifically says is not set.

Reported-by: Christina Smith <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e44a90c59697cf98e05619fbb6f77a403d347495
      
https://github.com/qemu/qemu/commit/e44a90c59697cf98e05619fbb6f77a403d347495
  Author: Alex Bennée <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: fix unallocated test of scalar SQXTUN

The test for the U bit was incorrectly inverted in the scalar case of SQXTUN.
This doesn't affect the vector case as the U bit is used to select XTN(2).

Reported-by: Hao Liu <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Claudio Fontana <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2d03b49c3f225994c4b0b46146437d8c887d6774
      
https://github.com/qemu/qemu/commit/2d03b49c3f225994c4b0b46146437d8c887d6774
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-17 (Thu, 17 Apr 2014)

  Changed paths:
    M hw/arm/cubieboard.c
    M hw/intc/allwinner-a10-pic.c
    M hw/misc/zynq_slcr.c
    M hw/net/allwinner_emac.c
    M hw/net/cadence_gem.c
    M hw/timer/allwinner-a10-pit.c
    M hw/timer/cadence_ttc.c
    M include/exec/softmmu_exec.h
    M include/hw/net/allwinner_emac.h
    M include/hw/timer/allwinner-a10-pit.h
    M linux-user/main.c
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/gdbstub64.c
    M target-arm/helper-a64.c
    M target-arm/helper.c
    M target-arm/helper.h
    A target-arm/internals.h
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/machine.c
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20140417-1' into staging

target-arm queue:
 * AArch64 system mode support; this is all the CPU emulation code
   but not the virt board support
 * cadence_ttc match register bugfix
 * Allwinner A10 PIC, PIT and ethernet fixes
   [with update to avoid duplicate typedef]
 * zynq-slcr rewrite
 * cadence_gem bugfix
 * fix for SMLALD/SMLSLD insn in A32
 * fix for SQXTUN in A64

# gpg: Signature made Thu 17 Apr 2014 21:35:57 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140417-1: (51 commits)
  target-arm: A64: fix unallocated test of scalar SQXTUN
  arm: translate.c: Fix smlald Instruction
  net: cadence_gem: Make phy respond to broadcast
  misc: zynq_slcr: Make DB_PRINTs always compile
  misc: zynq_slcr: Convert SBD::init to object init
  misc: zynq-slcr: Rewrite
  allwinner-emac: update irq status after writes to interrupt registers
  allwinner-emac: set autonegotiation complete bit on link up
  allwinner-a10-pit: implement prescaler and source selection
  allwinner-a10-pit: use level triggered interrupts
  allwinner-a10-pit: avoid generation of spurious interrupts
  allwinner-a10-pic: fix behaviour of pending register
  allwinner-a10-pic: set vector address when an interrupt is pending
  timer: cadence_ttc: Fix match register write logic
  target-arm/gdbstub64.c: remove useless 'break' statement.
  target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32
  target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc
  target-arm: Make Cortex-A15 CBAR read-only
  target-arm: Implement CBAR for Cortex-A57
  target-arm: Implement Cortex-A57 implementation-defined system registers
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c6138aabfb2a...2d03b49c3f22