[Qemu-commits] [qemu/qemu] 1ecc3a: Pass semihosting exit code back to system.

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 1ecc3a2df168034b8ab33ff5ba6434ce3593dbb5
      
https://github.com/qemu/qemu/commit/1ecc3a2df168034b8ab33ff5ba6434ce3593dbb5
  Author: Liviu Ionescu <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/arm-semi.c

  Log Message:
  -----------
  Pass semihosting exit code back to system.

In order to run unit tests under semihosting, it is necessary to pass the
application exit code back to the system.

ARM defines only the code to be used for non-error application exit
(ADP_Stopped_ApplicationExit), all other codes should return non-zero
exit codes.

This patch checks if the application code passed via TARGET_SYS_EXIT is
ADP_Stopped_ApplicationExit, and return 0, otherwise return 1.

Signed-off-by: Liviu Ionescu <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a38bb0792ca8b4082d81884a6cb25fa0d334b4a6
      
https://github.com/qemu/qemu/commit/a38bb0792ca8b4082d81884a6cb25fa0d334b4a6
  Author: Liviu Ionescu <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M gdbstub.c
    M include/exec/gdbstub.h
    M qemu-options.hx
    M vl.c

  Log Message:
  -----------
  Add the "-semihosting-config" option.

The usual semihosting behaviour is to process the system calls locally and
return; unfortuantelly the initial implementation dinamically changed the
target to GDB during debug sessions, which, for the usual arm-none-eabi-gdb,
is not implemented. The result was that during debug sessions the semihosting
calls were discarded.

This patch adds a configuration variable and an option to set it on the
command line:

    -semihosting-config [enable=on|off,]target=native|gdb|auto

This option enables semihosting and defines where the semihosting calls will
be addressed, to QEMU ('native') or to GDB ('gdb'). The default is auto, which
means 'gdb' during debug sessions and 'native' otherwise.

Signed-off-by: Liviu Ionescu <address@hidden>
Message-id: address@hidden
[PMM: moved declaration and definition of semihosting_target to
 gdbstub.h and gdbstub.c to fix build failure on linux-user]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 57e3a0c7cb0ac2f0288890482e0a463adce2080a
      
https://github.com/qemu/qemu/commit/57e3a0c7cb0ac2f0288890482e0a463adce2080a
  Author: Greg Bellows <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: extend async excp masking

This patch extends arm_excp_unmasked() to use lookup tables for determining
whether IRQ and FIQ exceptions are masked.  The lookup tables are based on the
ARMv8 and ARMv7 specification physical interrupt masking tables.

If EL3 is using AArch64 IRQ/FIQ masking is ignored in all exception levels
other than EL3 if SCR.{FIQ|IRQ} is set to 1 (routed to EL3).

Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0eeb17d618361a0f4faddc160e33598b23da6dd5
      
https://github.com/qemu/qemu/commit/0eeb17d618361a0f4faddc160e33598b23da6dd5
  Author: Greg Bellows <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: add async excp target_el function

Adds a dedicated function and a lookup table for determining the target
exception level of IRQ and FIQ exceptions.  The lookup table is taken from the
ARMv7 and ARMv8 specification exception routing tables.

Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ea30a4b824ecc3c829b70eb9999ac5457dc5790f
      
https://github.com/qemu/qemu/commit/ea30a4b824ecc3c829b70eb9999ac5457dc5790f
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: add banked register accessors

If EL3 is in AArch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used.

- A32_BANKED macros are used for choosing the banked register based on provided
  input security argument.  This macro is used to choose the bank during
  translation of MRC/MCR instructions that are dependent on something other
  than the current secure state.
- A32_BANKED_CURRENT macros are used for choosing the banked register based on
  current secure state.  This is NOT to be used for choosing the bank used
  during translation as it breaks monitor mode.

If EL3 is operating in AArch64 state coprocessor registers are not
banked anymore. The macros use the non-secure instance (_ns) in this
case, which is architecturally mapped to the AArch64 EL register.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3f342b9e0e64ad681cd39840bfa75ef12d2807c1
      
https://github.com/qemu/qemu/commit/3f342b9e0e64ad681cd39840bfa75ef12d2807c1
  Author: Sergey Fedorov <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: add non-secure Translation Block flag

This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
Johannes Winter <address@hidden>.

The TBFLAG captures the SCR NS secure state at the time when a TB is created so
the correct bank is accessed on system register accesses.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c3e302606253a17568dc3ef30238f102468f7ee1
      
https://github.com/qemu/qemu/commit/c3e302606253a17568dc3ef30238f102468f7ee1
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: add CPREG secure state support

Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).

Also added secure state tracking field and flags.  This allows for
identification of the register info secure state.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 51a79b039728277e35fd19f7a7b4bc6cb323697f
      
https://github.com/qemu/qemu/commit/51a79b039728277e35fd19f7a7b4bc6cb323697f
  Author: Peter Maydell <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/kvm32.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: add secure state bit to CPREG hash

Added additional NS-bit to CPREG hash encoding.  Updated hash lookup
locations to specify hash bit currently set to non-secure.

Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: fix uses of ENCODE_CP_REG in kvm32.c to add extra argument]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3f3c82a57d128aa3ec823aa8032867c3a6e2e795
      
https://github.com/qemu/qemu/commit/3f3c82a57d128aa3ec823aa8032867c3a6e2e795
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: insert AArch32 cpregs twice into hashtable

Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0f1a3b2470d798ad5335eb9d6236f02ff64e31a8
      
https://github.com/qemu/qemu/commit/0f1a3b2470d798ad5335eb9d6236f02ff64e31a8
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: move AArch32 SCR into security reglist

Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving AArch32 SCR into Security Extension register group.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: de38d23b542efca54108ef28bcc0efe96f378d2e
      
https://github.com/qemu/qemu/commit/de38d23b542efca54108ef28bcc0efe96f378d2e
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: implement IRQ/FIQ routing to Monitor mode

SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 770225764f831031d2e1453f69c365eb1b647d87
      
https://github.com/qemu/qemu/commit/770225764f831031d2e1453f69c365eb1b647d87
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: add NSACR register

Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 144634ae6c1618dcee6aced9c0d4427844154091
      
https://github.com/qemu/qemu/commit/144634ae6c1618dcee6aced9c0d4427844154091
  Author: Greg Bellows <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: add SDER definition

Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for
register storage.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e89e51a17ea0d8aef9bf9b766c98f963e835fbf2
      
https://github.com/qemu/qemu/commit/e89e51a17ea0d8aef9bf9b766c98f963e835fbf2
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: add MVBAR support

Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 137feaa9a1622620adf19c0b707883dd990738e2
      
https://github.com/qemu/qemu/commit/137feaa9a1622620adf19c0b707883dd990738e2
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M hw/arm/pxa2xx.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: add SCTLR_EL3 and make SCTLR banked

Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6e8801f9dea9e10449f4fd7d85dbe8cab708a686
      
https://github.com/qemu/qemu/commit/6e8801f9dea9e10449f4fd7d85dbe8cab708a686
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI

Add checks of SCR AW/FW bits when performing writes of CPSR.  These SCR bits
are used to control whether the CPSR masking bits can be adjusted from
non-secure state.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b85a1fd61c4d72c7928cd9b70f9f59fb2895936d
      
https://github.com/qemu/qemu/commit/b85a1fd61c4d72c7928cd9b70f9f59fb2895936d
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: make CSSELR banked

Rename CSSELR (cache size selection register) and add secure
instance (AArch32).

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc
      
https://github.com/qemu/qemu/commit/7dd8c9af0d9d18fb3e54a4843b3bb1398bd330bc
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M hw/arm/pxa2xx.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: make TTBR0/1 banked

Adds secure and non-secure bank register suport for TTBR0 and TTBR1.
Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as
well as a CP register definition for TTBR0_EL3.  Added a union containing
both EL based array fields and secure and non-secure fields mapped to them.
Updated accesses to use A32_BANKED_CURRENT_REG_GET macro.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 11f136ee25232a00f433cefe98ee33cd614ecccc
      
https://github.com/qemu/qemu/commit/11f136ee25232a00f433cefe98ee33cd614ecccc
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/internals.h

  Log Message:
  -----------
  target-arm: make TTBCR banked

Adds secure and non-secure bank register suport for TTBCR.
Added new struct to compartmentalize the TCR data and masks.  Removed old
tcr/ttbcr data and added a 4 element array of the new structs in cp15.  This
allows for one entry per EL.  Added a CP register definition for TCR_EL3.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c17d68c1d3d6c35f37f5692042d2edb65c8bcc0
      
https://github.com/qemu/qemu/commit/0c17d68c1d3d6c35f37f5692042d2edb65c8bcc0
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M hw/arm/pxa2xx.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: make DACR banked

When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance.  Adds definition for DACR32_EL2.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 88ca1c2d70523486a952065f3ed7b8fc823b5863
      
https://github.com/qemu/qemu/commit/88ca1c2d70523486a952065f3ed7b8fc823b5863
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: make IFSR banked

When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance.  Adds IFSR32_EL2 definition and
storage.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4a7e2d7315bd2ce28e49ccd0bde73eabdfd7437b
      
https://github.com/qemu/qemu/commit/4a7e2d7315bd2ce28e49ccd0bde73eabdfd7437b
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: make DFSR banked

When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b848ce2b9cbd38da3f2530fd93dba76dba0621c0
      
https://github.com/qemu/qemu/commit/b848ce2b9cbd38da3f2530fd93dba76dba0621c0
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: make IFAR/DFAR banked

When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 01c097f7960b330c4bf038d34bae17ad6c1ba499
      
https://github.com/qemu/qemu/commit/01c097f7960b330c4bf038d34bae17ad6c1ba499
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: make PAR banked

When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fb6c91ba2bb0b1c1b8662ceeeeb9474a025f9a6b
      
https://github.com/qemu/qemu/commit/fb6c91ba2bb0b1c1b8662ceeeeb9474a025f9a6b
  Author: Greg Bellows <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: make VBAR banked

When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 54bf36ed351c526cde0c853079f9ff1ab7e2ff89
      
https://github.com/qemu/qemu/commit/54bf36ed351c526cde0c853079f9ff1ab7e2ff89
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M linux-user/aarch64/target_cpu.h
    M linux-user/arm/target_cpu.h
    M linux-user/main.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: make c13 cp regs banked (FCSEIDR, ...)

When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: be693c87e440e671ed913784554384349ce8331d
      
https://github.com/qemu/qemu/commit/be693c87e440e671ed913784554384349ce8331d
  Author: Greg Bellows <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: make MAIR0/1 banked

Added CP register info entries for the ARMv7 MAIR0/1 secure banks.

Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b1ab03af890b2b6c5bafc9344b7fe05b392180a5
      
https://github.com/qemu/qemu/commit/b1ab03af890b2b6c5bafc9344b7fe05b392180a5
  Author: Nikita Belov <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M hw/arm/realview.c

  Log Message:
  -----------
  hw/arm/realview.c: Fix memory leak in realview_init()

Variable 'ram_lo' is allocated unconditionally, but used only in some cases.
When it is unused pointer will be lost at function exit, resulting in a
memory leak. Allocate memory for 'ram_lo' only if it is needed.

Valgrind output:
==16879== 240 bytes in 1 blocks are definitely lost in loss record 6,033 of 
7,018
==16879==    at 0x4C2AB80: malloc (in 
/usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==16879==    by 0x33D2CE: malloc_and_trace (vl.c:2804)
==16879==    by 0x509E610: g_malloc (in 
/lib/x86_64-linux-gnu/libglib-2.0.so.0.4000.0)
==16879==    by 0x288836: realview_init (realview.c:55)
==16879==    by 0x28988C: realview_pb_a8_init (realview.c:375)
==16879==    by 0x341426: main (vl.c:4413)

Signed-off-by: Nikita Belov <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a554ecb49d0021fd8bb0fd4f2f6be807b3c8b54f
      
https://github.com/qemu/qemu/commit/a554ecb49d0021fd8bb0fd4f2f6be807b3c8b54f
  Author: zhanghailiang <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: fix uninitialized scalar variable warning reported by coverity

Coverity reports the 'size' may be used uninitialized, but that can't happen,
because the caller has checked "if (binfo->dtb_filename || binfo->get_dtb)"
before call 'load_dtb'.

Here we simply remove the 'if (binfo->get_dtb)' to satisfy coverity.

Signed-off-by: zhanghailiang <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 72149414e25784de60b821fe67c56108a5b03ce1
      
https://github.com/qemu/qemu/commit/72149414e25784de60b821fe67c56108a5b03ce1
  Author: Peter Maydell <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M hw/intc/arm_gic_kvm.c

  Log Message:
  -----------
  arm_gic_kvm: Tell kernel about number of IRQs

Newer kernels support a device attribute on the GIC which allows us to
tell it how many IRQs this GIC instance is configured with; use it, if
it exists.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christoffer Dall <address@hidden>
Message-id: address@hidden


  Commit: 38df27c8a7ef9877583a46e74d99181c3224e078
      
https://github.com/qemu/qemu/commit/38df27c8a7ef9877583a46e74d99181c3224e078
  Author: Alex Bennée <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/kvm.c
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/kvm_arm.h

  Log Message:
  -----------
  target-arm/kvm: make reg sync code common between kvm32/64

Before we launch a guest we query KVM for the list of "co-processor"
registers it knows about. This is used to synchronize system
register state for the bulk of coprocessor/system registers.
Move this code from the 32-bit specific vcpu init function into
a common routine and call it also from the 64-bit vcpu init.

This allows system registers to migrate correctly when using
KVM, and also permits QEMU code to see the current KVM register
state (which will be needed to support big-endian guests, since
the virtio endianness callback must check for some system register
settings).

Since vcpu reset also has to sync registers, we move the
32 bit kvm_arm_reset_vcpu() into common code as well and
share it with the 64 bit version.

Signed-off-by: Alex Bennée <address@hidden>
[PMM: just copy the 32-bit code rather than improving it along the way;
 don't share reg_syncs_via_tuple_list() between 32 and 64 bit;
 tweak function names; move reset]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a7130a3ef9b8dc3091a0700abb61e2926e89e916
      
https://github.com/qemu/qemu/commit/a7130a3ef9b8dc3091a0700abb61e2926e89e916
  Author: Peter Maydell <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: Support save/load for 64 bit CPUs

For migration to work on 64 bit CPUs, we need to include both
the 64-bit integer register file and the PSTATE. Everything
else is either stored in the same place as existing 32-bit CPU
state or handled by the generic sysreg mechanism.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 25f2895e0e437a3548f9794846001fb5d5ab853d
      
https://github.com/qemu/qemu/commit/25f2895e0e437a3548f9794846001fb5d5ab853d
  Author: Christoffer Dall <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-arm/kvm.c

  Log Message:
  -----------
  target-arm: Check error conditions on kvm_arm_reset_vcpu

When resetting a VCPU we currently call both kvm_arm_vcpu_init() and
write_kvmstate_to_list(), both of which can fail, but we never check the
return value.

The only choice here is to print an error an exit if the calls fail.

Signed-off-by: Christoffer Dall <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b141290478f847ecaa25561f3b31fbf1ddde95e6
      
https://github.com/qemu/qemu/commit/b141290478f847ecaa25561f3b31fbf1ddde95e6
  Author: Peter Maydell <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M gdbstub.c
    M hw/arm/boot.c
    M hw/arm/pxa2xx.c
    M hw/arm/realview.c
    M hw/intc/arm_gic_kvm.c
    M include/exec/gdbstub.h
    M linux-user/aarch64/target_cpu.h
    M linux-user/arm/target_cpu.h
    M linux-user/main.c
    M qemu-options.hx
    M target-arm/arm-semi.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/kvm.c
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/kvm_arm.h
    M target-arm/machine.c
    M target-arm/op_helper.c
    M target-arm/translate.c
    M target-arm/translate.h
    M vl.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20141211' 
into staging

target-arm queue:
 * pass semihosting exit code out to system
 * more TrustZone support code (still not enabled yet)
 * allow user to direct semihosting to gdb or native explicitly
   rather than always auto-guessing the destination
 * fix memory leak in realview_init
 * fix coverity warning in hw/arm/boot
 * get state migration working for AArch64 CPUs
 * check errors in kvm_arm_reset_vcpu

# gpg: Signature made Thu 11 Dec 2014 12:16:19 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20141211: (33 commits)
  target-arm: Check error conditions on kvm_arm_reset_vcpu
  target-arm: Support save/load for 64 bit CPUs
  target-arm/kvm: make reg sync code common between kvm32/64
  arm_gic_kvm: Tell kernel about number of IRQs
  hw/arm/boot: fix uninitialized scalar variable warning reported by coverity
  hw/arm/realview.c: Fix memory leak in realview_init()
  target-arm: make MAIR0/1 banked
  target-arm: make c13 cp regs banked (FCSEIDR, ...)
  target-arm: make VBAR banked
  target-arm: make PAR banked
  target-arm: make IFAR/DFAR banked
  target-arm: make DFSR banked
  target-arm: make IFSR banked
  target-arm: make DACR banked
  target-arm: make TTBCR banked
  target-arm: make TTBR0/1 banked
  target-arm: make CSSELR banked
  target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI
  target-arm: add SCTLR_EL3 and make SCTLR banked
  target-arm: add MVBAR support
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/7c3843332db3...b141290478f8