[Qemu-commits] [qemu/qemu] f0cab0: target-tricore: Fix RLC_ADDI, RLC_ADDIH using wron...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: f0cab01b6c9bb9c2f5085837ca86d70d144cca9d
      
https://github.com/qemu/qemu/commit/f0cab01b6c9bb9c2f5085837ca86d70d144cca9d
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-03-03 (Tue, 03 Mar 2015)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 3debbb5af5f63440b170b71bf3aecc0e778f5691
      
https://github.com/qemu/qemu/commit/3debbb5af5f63440b170b71bf3aecc0e778f5691
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-03-03 (Tue, 03 Mar 2015)

  Changed paths:
    M target-tricore/op_helper.c

  Log Message:
  -----------
  target-tricore: fix msub32_suov return wrong results

If the signed result of the multiplication overflows, we would get a negative
value, which would result in a addition instead of a subtraction.

Now we do the overflow calculation and saturation by hand instead of using
suov32_neg.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 2984cfbdb4dbc31d614aaa0303374dff951e7a31
      
https://github.com/qemu/qemu/commit/2984cfbdb4dbc31d614aaa0303374dff951e7a31
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-03-03 (Tue, 03 Mar 2015)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of RRR2 opcode format

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 2e430e1cdcbac8825bc44b42844cbb011b859847
      
https://github.com/qemu/qemu/commit/2e430e1cdcbac8825bc44b42844cbb011b859847
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-03-03 (Tue, 03 Mar 2015)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as 
first opcode

Add helpers:
    * add64_ssov: adds two 64 bit values and saturates the result.
    * addr_h/_ssov: adds two halfwords with two words in q-format with rounding
              / and saturates each result independetly.

Add microcode generator:
    * gen_add64_d: adds two 64 bit values.
    * gen_addsub64_h: adds/subtracts one halfwords with a word and adds/
                subtracts another halftword with another word.
    * gen_madd_h/s_h: multiply four halfwords, add each result left justfied
                to two word values / and saturate each result.
    * gen_maddm_h/s_h: multiply four halfwords, add each result left justfied
                 to two words values in q-format / and saturate each
                 result.
    * gen_maddr32/64_h/s_h: multiply four halfwords, add each result left
                      justfied to two halftwords/words values in q-format
                      / and saturate each result.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: b00aa8ecbc6fd7468178a0dabc7dfd0b7e1b8cd6
      
https://github.com/qemu/qemu/commit/b00aa8ecbc6fd7468178a0dabc7dfd0b7e1b8cd6
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-03-03 (Tue, 03 Mar 2015)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as 
first opcode

Add helpers:
    * madd64_q_ssov: multiply two 32 bit q-format number, add them with a
               64 bit q-format number and saturate.
    * madd32_q_add_ssov: add two 64 bit q-format numbers and return a 32 bit
                   result.
    * maddr_q_ssov: multiplay two 32 bit q-format numbers, add a 32 bit
              q-format number and saturate.
    * maddr_q: multiplay two 32 bit q-format numbers and add a 32 bit
         q-format number.

Note: madd instructions in the q format can behave strange, e.g.
0x1 + (0x80000000 * 0x80000000) << 1 for 32 bit signed values does not cause an
overflow on the guest, because all intermediate results should be handled as if
they are indefinitely precise. We handle this by inverting the overflow bit for
all cases: a + (0x80000000 * 0x80000000) << 1.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: bebe80fc78cc91c4225cfb98ef3a916b9c861c60
      
https://github.com/qemu/qemu/commit/bebe80fc78cc91c4225cfb98ef3a916b9c861c60
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-03-03 (Tue, 03 Mar 2015)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as 
first opcode

Add helpers helper_addsur_h/_ssov which adds one halfword and subtracts one
halfword, rounds / and saturates each half word independently.

Add microcode helper functions:
    * gen_maddsu_h/sus_h: multiply two halfwords left justified and add to the
                    first one word and subtract from the second one word
                    / and saturate each resulting word independetly.
    * gen_maddsum_h/sums_h: multiply two halfwords in q-format left justified
                      and add to the first one word and subtract from
                      the second one word / and saturate each resulting
                      word independetly.
    * gen_maddsur32_h/32s_h: multiply two halfwords in q-format left justified
                       and add to the first one word and subtract from
                       the second one word, round both results / and
                       saturate each resulting word independetly.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: cff6abd6f2fc1af588207b27f2a6b96e15bd96dc
      
https://github.com/qemu/qemu/commit/cff6abd6f2fc1af588207b27f2a6b96e15bd96dc
  Author: Peter Maydell <address@hidden>
  Date:   2015-03-08 (Sun, 08 Mar 2015)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150303' 
into staging

TriCore RRR1, RRR2 instructions and bugfixes

# gpg: Signature made Tue Mar  3 01:12:02 2015 GMT using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <address@hidden>"

* remotes/bkoppelmann/tags/pull-tricore-20150303:
  target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as 
first opcode
  target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as 
first opcode
  target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as 
first opcode
  target-tricore: Add instructions of RRR2 opcode format
  target-tricore: fix msub32_suov return wrong results
  target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c10b02836ff0...cff6abd6f2fc