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[Qemu-commits] [qemu/qemu] 71ca03: target-mips: move the test for enable

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 71ca03: target-mips: move the test for enabled interrupts ...
Date: Fri, 30 Oct 2015 11:00:06 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 71ca034a0dee69f77c8ac6ea7d21e5b6a0b0d836
      
https://github.com/qemu/qemu/commit/71ca034a0dee69f77c8ac6ea7d21e5b6a0b0d836
  Author: Leon Alrae <address@hidden>
  Date:   2015-10-29 (Thu, 29 Oct 2015)

  Changed paths:
    M target-mips/cpu.c
    M target-mips/cpu.h
    M target-mips/helper.c

  Log Message:
  -----------
  target-mips: move the test for enabled interrupts to a separate function

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 7540a43a1d9de71fa7a53ccd2bb24a04e2aace41
      
https://github.com/qemu/qemu/commit/7540a43a1d9de71fa7a53ccd2bb24a04e2aace41
  Author: Leon Alrae <address@hidden>
  Date:   2015-10-29 (Thu, 29 Oct 2015)

  Changed paths:
    M target-mips/cpu.c

  Log Message:
  -----------
  target-mips: implement the CPU wake-up on non-enabled interrupts in R6

In Release 6, the behaviour of WAIT has been modified to make it a
requirement that a processor that has disabled operation as a result of
executing a WAIT will resume operation on arrival of an interrupt even if
interrupts are not enabled.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 2dcf7908d9e0274c08911400beb7ed14276bb170
      
https://github.com/qemu/qemu/commit/2dcf7908d9e0274c08911400beb7ed14276bb170
  Author: Leon Alrae <address@hidden>
  Date:   2015-10-29 (Thu, 29 Oct 2015)

  Changed paths:
    M target-mips/cpu.h

  Log Message:
  -----------
  target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6

Implement the relationship between CP0.Status.KX, SX and UX. It should not
be possible to set UX bit if SX is 0, the same applies for setting SX if
KX is 0.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: dbd8af9824d0ddc4400f859c2af77543461cba0d
      
https://github.com/qemu/qemu/commit/dbd8af9824d0ddc4400f859c2af77543461cba0d
  Author: Yongbok Kim <address@hidden>
  Date:   2015-10-29 (Thu, 29 Oct 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Add enum for BREAK32

Add enum for BREAK32

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: ca2f6bbbce32b7e1ba4fdaf54165ab0dee47a3a5
      
https://github.com/qemu/qemu/commit/ca2f6bbbce32b7e1ba4fdaf54165ab0dee47a3a5
  Author: James Hogan <address@hidden>
  Date:   2015-10-30 (Fri, 30 Oct 2015)

  Changed paths:
    M hw/mips/mips_malta.c

  Log Message:
  -----------
  hw/mips_malta: Fix KVM PC initialisation

Commit 71c199c81d29 ("mips_malta: provide ememsize env variable to
kernels") changed the meaning of loaderparams.ram_size to be the whole
of RAM rather than just the low part below where the boot code is placed
for KVM, but it didn't update the PC initialisation for KVM to use
ram_low_size. Fix that now.

Fixes: 71c199c81d29 ("mips_malta: provide ememsize env variable to kernels")
Signed-off-by: James Hogan <address@hidden>
Cc: Paul Burton <address@hidden>
Cc: Leon Alrae <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: b00c72180c36510bf9b124e190bd520e3b7e1358
      
https://github.com/qemu/qemu/commit/b00c72180c36510bf9b124e190bd520e3b7e1358
  Author: Yongbok Kim <address@hidden>
  Date:   2015-10-30 (Fri, 30 Oct 2015)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add PC, XNP reg numbers to RDHWR

Add Performance Counter (4) and XNP (5) register numbers to RDHWR.
Add check_hwrena() to simplify access control checkings.
Add RDHWR support to microMIPS R6.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 35ac9e342e008e3d47ef18d33a6977fdb99de9cd
      
https://github.com/qemu/qemu/commit/35ac9e342e008e3d47ef18d33a6977fdb99de9cd
  Author: Yongbok Kim <address@hidden>
  Date:   2015-10-30 (Fri, 30 Oct 2015)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: Set Config5.XNP for R6 cores

Set Config5.XNP for R6 cores to indicate the extended LL/SC family
of instructions NOT present.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: bb238210bb096534b68dab15a87c6ff0bef43672
      
https://github.com/qemu/qemu/commit/bb238210bb096534b68dab15a87c6ff0bef43672
  Author: Yongbok Kim <address@hidden>
  Date:   2015-10-30 (Fri, 30 Oct 2015)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add SIGRIE instruction

Add SIGRIE (Signal Reserved Instruction Exception) for both MIPS and
microMIPS.
The instruction allows to use the 16-bit code field for software use.
This instruction is introduced by and required as of Release 6.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 60270f85cc93d2d34e45b7679c374b1d771f0eeb
      
https://github.com/qemu/qemu/commit/60270f85cc93d2d34e45b7679c374b1d771f0eeb
  Author: Yongbok Kim <address@hidden>
  Date:   2015-10-30 (Fri, 30 Oct 2015)

  Changed paths:
    M target-mips/helper.c

  Log Message:
  -----------
  target-mips: fix updating XContext on mmu exception

Correct updating XContext.Region field on mmu exceptions.
If Config3.CTXTC = 0 then the R field of XContext has to be updated
with the value of bits 63..62 of the virtual address upon a TLB
exception.
Also fixed the below line which overs 80 characters.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: James Hogan <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: e79ea9e4240971b43494184d68a7f5a67d07e74b
      
https://github.com/qemu/qemu/commit/e79ea9e4240971b43494184d68a7f5a67d07e74b
  Author: Peter Maydell <address@hidden>
  Date:   2015-10-30 (Fri, 30 Oct 2015)

  Changed paths:
    M hw/mips/mips_malta.c
    M target-mips/cpu.c
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20151030' into staging

MIPS patches 2015-10-30

Changes:
* R6 CPU can be woken up by non-enabled interrupts
* PC fix in KVM
* Coprocessor 0 XContext calculation fix
* various MIPS R6 updates

# gpg: Signature made Fri 30 Oct 2015 14:51:56 GMT using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <address@hidden>"

* remotes/lalrae/tags/mips-20151030:
  target-mips: fix updating XContext on mmu exception
  target-mips: add SIGRIE instruction
  target-mips: Set Config5.XNP for R6 cores
  target-mips: add PC, XNP reg numbers to RDHWR
  hw/mips_malta: Fix KVM PC initialisation
  target-mips: Add enum for BREAK32
  target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6
  target-mips: implement the CPU wake-up on non-enabled interrupts in R6
  target-mips: move the test for enabled interrupts to a separate function

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/fdf927621a99...e79ea9e42409
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