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[Qemu-commits] [qemu/qemu] a85959: hw/arm_gic: Correctly restore nested
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GitHub |
Subject: |
[Qemu-commits] [qemu/qemu] a85959: hw/arm_gic: Correctly restore nested irq priority |
Date: |
Thu, 19 Nov 2015 08:30:04 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: a859595791e6ac5c14afe0b8a53634bf1cc21f0f
https://github.com/qemu/qemu/commit/a859595791e6ac5c14afe0b8a53634bf1cc21f0f
Author: François Baldassari <address@hidden>
Date: 2015-11-19 (Thu, 19 Nov 2015)
Changed paths:
M hw/intc/arm_gic.c
Log Message:
-----------
hw/arm_gic: Correctly restore nested irq priority
Upon activating an interrupt, set the corresponding priority bit in the
APR/NSAPR registers without touching the currently set bits. In the event
of nested interrupts, the GIC will then have the information it needs to
restore the priority of the pre-empted interrupt once the higher priority
interrupt finishes execution.
Signed-off-by: François Baldassari <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 43bfa4a100687af8d293fef0a197839b51400fca
https://github.com/qemu/qemu/commit/43bfa4a100687af8d293fef0a197839b51400fca
Author: Sergey Fedorov <address@hidden>
Date: 2015-11-19 (Thu, 19 Nov 2015)
Changed paths:
M target-arm/translate.c
Log Message:
-----------
target-arm: Update condexec before CP access check in AA32 translation
Coprocessor access instructions are allowed inside IT block.
gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
bits should be updated before.
Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: ce8a1b5449cd8c4c2831abb581d3208c3a3745a0
https://github.com/qemu/qemu/commit/ce8a1b5449cd8c4c2831abb581d3208c3a3745a0
Author: Sergey Fedorov <address@hidden>
Date: 2015-11-19 (Thu, 19 Nov 2015)
Changed paths:
M target-arm/translate.c
Log Message:
-----------
target-arm: Update condexec before arch BP check in AA32 translation
Architectural breakpoint check could raise an exceptions, thus condexec
bits should be updated before calling gen_helper_check_breakpoints().
Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: c601a244a49f4e0be2539cbc5ffd288727cd4e89
https://github.com/qemu/qemu/commit/c601a244a49f4e0be2539cbc5ffd288727cd4e89
Author: Peter Maydell <address@hidden>
Date: 2015-11-19 (Thu, 19 Nov 2015)
Changed paths:
M hw/intc/arm_gic.c
M target-arm/translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151119'
into staging
target-arm queue:
* add missing condexec updates when emulating architectural breakpoints
and coprocessor access checks in Thumb translation (could in theory
cause problems when these happened inside a Thumb IT block and an
exception was taken)
* arm_gic: correctly restore nested IRQ priority
# gpg: Signature made Thu 19 Nov 2015 13:29:37 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
* remotes/pmaydell/tags/pull-target-arm-20151119:
target-arm: Update condexec before arch BP check in AA32 translation
target-arm: Update condexec before CP access check in AA32 translation
hw/arm_gic: Correctly restore nested irq priority
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/80fda8f60945...c601a244a49f
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