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[Qemu-commits] [qemu/qemu] 08944b: hw/mips_cmgcr: allow GCR base to be m

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 08944b: hw/mips_cmgcr: allow GCR base to be moved
Date: Thu, 23 Feb 2017 05:00:10 -0800 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 08944be1d91779aec4346cc569f87e4c915a944c
      
https://github.com/qemu/qemu/commit/08944be1d91779aec4346cc569f87e4c915a944c
  Author: Paul Burton <address@hidden>
  Date:   2017-02-21 (Tue, 21 Feb 2017)

  Changed paths:
    M hw/misc/mips_cmgcr.c
    M include/hw/misc/mips_cmgcr.h

  Log Message:
  -----------
  hw/mips_cmgcr: allow GCR base to be moved

Support moving the GCR base address & updating the CPU's CP0 CMGCRBase
register appropriately. This is required if a platform needs to move its
GCRs away from other memory, as the MIPS Boston development board does
to avoid its flash memory.

Signed-off-by: Paul Burton <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: eb90ab9437ebb2dea77ebdf6c96488841ddbdd85
      
https://github.com/qemu/qemu/commit/eb90ab9437ebb2dea77ebdf6c96488841ddbdd85
  Author: Paul Burton <address@hidden>
  Date:   2017-02-21 (Tue, 21 Feb 2017)

  Changed paths:
    M hw/timer/mips_gictimer.c
    M include/hw/timer/mips_gictimer.h

  Log Message:
  -----------
  hw/mips_gictimer: provide API for retrieving frequency

Provide a new function mips_gictimer_get_freq() which returns the
frequency at which a GIC timer will count. This will be useful for
boards which perform setup based upon this frequency.

Signed-off-by: Paul Burton <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 2e2a1b4648114ebbb371c10f31c66d10bcd40051
      
https://github.com/qemu/qemu/commit/2e2a1b4648114ebbb371c10f31c66d10bcd40051
  Author: Paul Burton <address@hidden>
  Date:   2017-02-21 (Tue, 21 Feb 2017)

  Changed paths:
    M hw/intc/mips_gic.c

  Log Message:
  -----------
  hw/mips_gic: Update pin state on mask changes

If the GIC interrupt mask is changed by a write to the smask (set mask)
or rmask (reset mask) registers, we need to re-evaluate the state of the
pins/IRQs fed to the CPU. Without doing so we risk leaving a pin high
despite the interrupt that led to that state being masked, or losing
interrupts if an already pending interrupt is unmasked.

Signed-off-by: Paul Burton <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: bed9e5ceb158c886d548fe59675a6eba18baeaeb
      
https://github.com/qemu/qemu/commit/bed9e5ceb158c886d548fe59675a6eba18baeaeb
  Author: Paul Burton <address@hidden>
  Date:   2017-02-21 (Tue, 21 Feb 2017)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/translate.c

  Log Message:
  -----------
  target-mips: Provide function to test if a CPU supports an ISA

Provide a new cpu_supports_isa function which allows callers to
determine whether a CPU supports one of the ISA_ flags, by testing
whether the associated struct mips_def_t sets the ISA flags in its
insn_flags field.

An example use of this is to allow boards which generate bootloader code
to determine the properties of the CPU that will be used, for example
whether the CPU is 64 bit or which architecture revision it implements.

Signed-off-by: Paul Burton <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 6e85fce0225f235b11618fe50eaec64c1de2cf3e
      
https://github.com/qemu/qemu/commit/6e85fce0225f235b11618fe50eaec64c1de2cf3e
  Author: Paul Burton <address@hidden>
  Date:   2017-02-21 (Tue, 21 Feb 2017)

  Changed paths:
    M configure
    M dtc

  Log Message:
  -----------
  dtc: Update requirement to v1.4.2

In order to obtain fdt_first_subnode & fdt_next_subnode symbols from
libfdt for use by a later patch, bump the requirement for dtc to v1.4.2
& the submodule to that same version.

Signed-off-by: Paul Burton <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 51b58561c1dacdb0ce999ada94912caaed157f83
      
https://github.com/qemu/qemu/commit/51b58561c1dacdb0ce999ada94912caaed157f83
  Author: Paul Burton <address@hidden>
  Date:   2017-02-21 (Tue, 21 Feb 2017)

  Changed paths:
    M hw/core/Makefile.objs
    A hw/core/loader-fit.c
    M hw/core/loader.c
    A include/hw/loader-fit.h
    M include/hw/loader.h

  Log Message:
  -----------
  loader: Support Flattened Image Trees (FIT images)

Introduce support for loading Flattened Image Trees, as used by modern
U-Boot. FIT images are essentially flattened device tree files which
contain binary images such as kernels, FDTs or ramdisks along with one
or more configuration nodes describing boot configurations.

The MIPS Boston board typically boots kernels in the form of FIT images,
and will make use of this code.

Signed-off-by: Paul Burton <address@hidden>
address@hidden:
  fixed potential memory leaks,
  isolated building option]
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 62be393423eac3d2fcb8313dc441db4e76f44c78
      
https://github.com/qemu/qemu/commit/62be393423eac3d2fcb8313dc441db4e76f44c78
  Author: Paul Burton <address@hidden>
  Date:   2017-02-21 (Tue, 21 Feb 2017)

  Changed paths:
    M hw/pci-host/Makefile.objs
    A hw/pci-host/xilinx-pcie.c
    A include/hw/pci-host/xilinx-pcie.h

  Log Message:
  -----------
  hw: xilinx-pcie: Add support for Xilinx AXI PCIe Controller

Add support for emulating the Xilinx AXI Root Port Bridge for PCI
Express as described by Xilinx' PG055 document. This is a PCIe
controller that can be used with certain series of Xilinx FPGAs, and is
used on the MIPS Boston board which will make use of this code.

Signed-off-by: Paul Burton <address@hidden>
address@hidden:
  removed returning on !level,
  updated IRQ connection with GPIO logic,
  moved xilinx_pcie_init() to boston.c
  replaced stw_le_p() with pci_set_word()
  and other cosmetic changes]
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: d3473e147a754e999718bf6fcb015d9978c6a1ee
      
https://github.com/qemu/qemu/commit/d3473e147a754e999718bf6fcb015d9978c6a1ee
  Author: Paul Burton <address@hidden>
  Date:   2017-02-21 (Tue, 21 Feb 2017)

  Changed paths:
    M configure
    M default-configs/mips64el-softmmu.mak
    M hw/mips/Makefile.objs
    A hw/mips/boston.c

  Log Message:
  -----------
  hw/mips: MIPS Boston board support

Introduce support for emulating the MIPS Boston development board. The
Boston board is built around an FPGA & 3 PCIe controllers, one of which
is connected to an Intel EG20T Platform Controller Hub. It is used
during the development & debug of new CPUs and the software intended to
run on them, and is essentially the successor to the older MIPS Malta
board.

This patch does not implement the EG20T, instead connecting an already
supported ICH-9 AHCI controller. Whilst this isn't accurate it's enough
for typical stock Boston software (eg. Linux kernels) to work with hard
disks given that both the ICH-9 & EG20T implement the AHCI
specification.

Boston boards typically boot kernels in the FIT image format, and this
patch will treat kernels provided to QEMU as such. When loading a kernel
directly, the board code will generate minimal firmware much as the
Malta board code does. This firmware will set up the CM, CPC & GIC
register base addresses then set argument registers & jump to the kernel
entry point. Alternatively, bootloader code may be loaded using the bios
argument in which case no firmware will be generated & execution will
proceed from the start of the boot code at the default MIPS boot
exception vector (offset 0x1fc00000 into (c)kseg1).

Currently real Boston boards are always used with FPGA bitfiles that
include a Global Interrupt Controller (GIC), so the interrupt
configuration is only defined for such cases. Therefore the board will
only allow use of CPUs which implement the CPS components, including the
GIC, and will otherwise exit with a message.

Signed-off-by: Paul Burton <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
address@hidden:
  isolated boston machine support for mips64el.
  updated for recent Chardev changes.
  ignore missing bios/kernel for qtest.
  added default -drive to if=ide explicitly]
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 10f25e4844cb9b3f02fb032f88051dd5b65b4206
      
https://github.com/qemu/qemu/commit/10f25e4844cb9b3f02fb032f88051dd5b65b4206
  Author: Peter Maydell <address@hidden>
  Date:   2017-02-23 (Thu, 23 Feb 2017)

  Changed paths:
    M configure
    M default-configs/mips64el-softmmu.mak
    M dtc
    M hw/core/Makefile.objs
    A hw/core/loader-fit.c
    M hw/core/loader.c
    M hw/intc/mips_gic.c
    M hw/mips/Makefile.objs
    A hw/mips/boston.c
    M hw/misc/mips_cmgcr.c
    M hw/pci-host/Makefile.objs
    A hw/pci-host/xilinx-pcie.c
    M hw/timer/mips_gictimer.c
    A include/hw/loader-fit.h
    M include/hw/loader.h
    M include/hw/misc/mips_cmgcr.h
    A include/hw/pci-host/xilinx-pcie.h
    M include/hw/timer/mips_gictimer.h
    M target/mips/cpu.h
    M target/mips/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170222' into staging

MIPS patches 2017-02-22

Changes:
* Add MIPS Boston board support

# gpg: Signature made Wed 22 Feb 2017 00:08:00 GMT
# gpg:                using RSA key 0x2238EB86D5F797C2
# gpg: Good signature from "Yongbok Kim <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA  2B5C 2238 EB86 D5F7 97C2

* remotes/yongbok/tags/mips-20170222:
  hw/mips: MIPS Boston board support
  hw: xilinx-pcie: Add support for Xilinx AXI PCIe Controller
  loader: Support Flattened Image Trees (FIT images)
  dtc: Update requirement to v1.4.2
  target-mips: Provide function to test if a CPU supports an ISA
  hw/mips_gic: Update pin state on mask changes
  hw/mips_gictimer: provide API for retrieving frequency
  hw/mips_cmgcr: allow GCR base to be moved

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e295a154c2a9...10f25e4844cb
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