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[Qemu-commits] [qemu/qemu] 00b707: target/ppc: move cpu_[read, write]_xe
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[Qemu-commits] [qemu/qemu] 00b707: target/ppc: move cpu_[read, write]_xer to cpu.c |
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Date: |
Thu, 02 Mar 2017 07:15:10 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 00b707883163de5c7daff2ab52fc39c7ecc05e92
https://github.com/qemu/qemu/commit/00b707883163de5c7daff2ab52fc39c7ecc05e92
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/Makefile.objs
A target/ppc/cpu.c
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: move cpu_[read, write]_xer to cpu.c
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1bd33d0d7cc47bed75e14f2cea3c7253f8017495
https://github.com/qemu/qemu/commit/1bd33d0d7cc47bed75e14f2cea3c7253f8017495
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: optimize gen_write_xer()
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 089f7e827de44532f71c560efede395ed72a087c
https://github.com/qemu/qemu/commit/089f7e827de44532f71c560efede395ed72a087c
Author: Laurent Vivier <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M include/hw/pci/pci_ids.h
Log Message:
-----------
PCI: add missing classes in pci_ids.h to build device tree
To allow QEMU to add PCI entries in device tree,
we must have a more exhaustive list of PCI class IDs.
This patch synchronizes as much as possible with
pci_ids.h and add some missing IDs from SLOF.
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2530a1a5cf20693ab8ff779ad9d0fb5f12788fa3
https://github.com/qemu/qemu/commit/2530a1a5cf20693ab8ff779ad9d0fb5f12788fa3
Author: Laurent Vivier <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr: generate DT node names
When DT node names for PCI devices are generated by SLOF,
they are generated according to the type of the device
(for instance, ethernet for virtio-net-pci device).
Node name for hotplugged devices is generated by QEMU.
This patch adds the mechanic to QEMU to create the node
name according to the device type too.
The data structure has been roughly copied from OpenBIOS/OpenHackware,
node names from SLOF.
Example:
Hotplugging some PCI cards with QEMU monitor:
device_add virtio-tablet-pci
device_add virtio-serial-pci
device_add virtio-mouse-pci
device_add virtio-scsi-pci
device_add virtio-gpu-pci
device_add ne2k_pci
device_add nec-usb-xhci
device_add intel-hda
What we can see in linux device tree:
for dir in /proc/device-tree/address@hidden/address@hidden/; do
echo $dir
cat $dir/name
echo
done
WITHOUT this patch:
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
/proc/device-tree/address@hidden/address@hidden/
pci
WITH this patch:
/proc/device-tree/address@hidden/address@hidden/
communication-controller
/proc/device-tree/address@hidden/address@hidden/
display
/proc/device-tree/address@hidden/address@hidden/
ethernet
/proc/device-tree/address@hidden/address@hidden/
input-controller
/proc/device-tree/address@hidden/address@hidden/
mouse
/proc/device-tree/address@hidden/address@hidden/
multimedia-device
/proc/device-tree/address@hidden/address@hidden/
scsi
/proc/device-tree/address@hidden/address@hidden/
usb-xhci
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f32899de97fc35d0de5f66e762d1a05707f104cd
https://github.com/qemu/qemu/commit/f32899de97fc35d0de5f66e762d1a05707f104cd
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/int_helper.c
Log Message:
-----------
target/ppc: introduce helper_update_ov_legacy
Removes duplicate code and will be useful for consolidating flags
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6244bb7e5811ff689688ab7ee8e8a7ced1c85010
https://github.com/qemu/qemu/commit/6244bb7e5811ff689688ab7ee8e8a7ced1c85010
Author: Greg Kurz <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
sysemu: support up to 1024 vCPUs
Some systems can already provide more than 255 hardware threads.
Bumping the QEMU limit to 1024 seems reasonable:
- it has no visible overhead in top;
- the limit itself has no effect on hot paths.
Cc: Greg Kurz <address@hidden>
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1ad9f0a464fe78d30ee60b3629f7a825cf2fab13
https://github.com/qemu/qemu/commit/1ad9f0a464fe78d30ee60b3629f7a825cf2fab13
Author: David Gibson <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/cpu.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
Log Message:
-----------
target/ppc: Fix KVM-HV HPTE accessors
When a 'pseries' guest is running with KVM-HV, the guest's hashed page
table (HPT) is stored within the host kernel, so it is not directly
accessible to qemu. Most of the time, qemu doesn't need to access it:
we're using the hardware MMU, and KVM itself implements the guest
hypercalls for manipulating the HPT.
However, qemu does need access to the in-KVM HPT to implement
get_phys_page_debug() for the benefit of the gdbstub, and maybe for
other debug operations.
To allow this, 7c43bca "target-ppc: Fix page table lookup with kvm
enabled" added kvmppc_hash64_read_pteg() to target/ppc/kvm.c to read
in a batch of HPTEs from the KVM table. Unfortunately, there are a
couple of problems with this:
First, the name of the function implies it always reads a whole PTEG
from the HPT, but in fact in some cases it's used to grab individual
HPTEs (which ends up pulling 8 HPTEs, not aligned to a PTEG from the
kernel).
Second, and more importantly, the code to read the HPTEs from KVM is
simply wrong, in general. The data from the fd that KVM provides is
designed mostly for compact migration rather than this sort of one-off
access, and so needs some decoding for this purpose. The current code
will work in some cases, but if there are invalid HPTEs then it will
not get sane results.
This patch rewrite the HPTE reading function to have a simpler
interface (just read n HPTEs into a caller provided buffer), and to
correctly decode the stream from the kernel.
For consistency we also clean up the similar function for altering
HPTEs within KVM (introduced in c138593 "target-ppc: Update
ppc_hash64_store_hpte to support updating in-kernel htab").
Cc: Aneesh Kumar K.V <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c6404adebf923fdd9ee5edf92594dcf5df3b5b10
https://github.com/qemu/qemu/commit/c6404adebf923fdd9ee5edf92594dcf5df3b5b10
Author: David Gibson <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
pseries: Minor cleanups to HPT management hypercalls
* Standardize on 'ptex' instead of 'pte_index' for HPTE index variables
for consistency and brevity
* Avoid variables named 'index'; shadowing index(3) from libc can lead to
surprising bugs if the variable is removed, because compiler errors
might not appear for remaining references
* Clarify index calculations in h_enter() - we have two cases, H_EXACT
where the exact HPTE slot is given, and !H_EXACT where we search for
an empty slot within the hash bucket. Make the calculation more
consistent between the cases.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Suraj Jitindar Singh <address@hidden>
Commit: b7b0b1f13a9d0b77b3dcb7696de420c2e805ca25
https://github.com/qemu/qemu/commit/b7b0b1f13a9d0b77b3dcb7696de420c2e805ca25
Author: David Gibson <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/ppc/spapr_cpu_core.c
M target/ppc/cpu.h
M target/ppc/translate_init.c
Log Message:
-----------
target/ppc: Merge cpu_ppc_set_vhyp() with cpu_ppc_set_papr()
cpu_ppc_set_papr() sets up various aspects of CPU state for use with PAPR
paravirtualized guests. However, it doesn't set the virtual hypervisor,
so callers must also call cpu_ppc_set_vhyp() so that PAPR hypercalls are
handled properly. This is a bit silly, so fold setting the virtual
hypervisor into cpu_ppc_set_papr().
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Suraj Jitindar Singh <address@hidden>
Commit: 7d6250e3d1a145e5427f21f5664995e0056b34a6
https://github.com/qemu/qemu/commit/7d6250e3d1a145e5427f21f5664995e0056b34a6
Author: David Gibson <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/misc_helper.c
M target/ppc/translate_init.c
Log Message:
-----------
target/ppc: SDR1 is a hypervisor resource
At present the SDR1 register - the base of the system's hashed page table
(HPT) - is represented as an SPR with supervisor read and write permission.
However, on CPUs which have a hypervisor mode, the SDR1 is a hypervisor
only resource. Change the permission checking on the SPR to reflect this.
Now that this is done, we don't need to check for an external HPT executing
mtsdr1: an external HPT only applies when we're emulating the behaviour of
a hypervisor, rather than modelling the CPU's hypervisor mode internally,
so if we're permitted to execute mtsdr1, we don't have an external HPT.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Suraj Jitindar Singh <address@hidden>
Commit: 7222b94a834e9f6ed99e55eb700cf492d61ba184
https://github.com/qemu/qemu/commit/7222b94a834e9f6ed99e55eb700cf492d61ba184
Author: David Gibson <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/ppc/spapr_hcall.c
M target/ppc/cpu.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
Log Message:
-----------
target/ppc: Cleanup HPTE accessors for 64-bit hash MMU
Accesses to the hashed page table (HPT) are complicated by the fact that
the HPT could be in one of three places:
1) Within guest memory - when we're emulating a full guest CPU at the
hardware level (e.g. powernv, mac99, g3beige)
2) Within qemu, but outside guest memory - when we're emulating user and
supervisor instructions within TCG, but instead of emulating
the CPU's hypervisor mode, we just emulate a hypervisor's behaviour
(pseries in TCG or KVM-PR)
3) Within the host kernel - a pseries machine using KVM-HV
acceleration. Mostly accesses to the HPT are handled by KVM,
but there are a few cases where qemu needs to access it via a
special fd for the purpose.
In order to batch accesses to the fd in case (3), we use a somewhat awkward
ppc_hash64_start_access() / ppc_hash64_stop_access() pair, which for case
(3) reads / releases several HPTEs from the kernel as a batch (usually a
whole PTEG). For cases (1) & (2) it just returns an address value. The
actual HPTE load helpers then need to interpret the returned token
differently in the 3 cases.
This patch keeps the same basic structure, but simplfiies the details.
First start_access() / stop_access() are renamed to map_hptes() and
unmap_hptes() to make their operation more obvious. Second, map_hptes()
now always returns a qemu pointer, which can always be used in the same way
by the load_hpte() helpers. In case (1) it comes from address_space_map()
in case (2) directly from qemu's HPT buffer and in case (3) from a
temporary buffer read from the KVM fd.
While we're at it, make things a bit more consistent in terms of types and
variable names: avoid variables named 'index' (it shadows index(3) which
can lead to confusing results), use 'hwaddr ptex' for HPTE indices and
uint64_t for each of the HPTE words, use ptex throughout the call stack
instead of pte_offset in some places (we still need that at the bottom
layer, but nowhere else).
Signed-off-by: David Gibson <address@hidden>
Commit: 36778660d7fd0748a6129916e47ecedd67bdb758
https://github.com/qemu/qemu/commit/36778660d7fd0748a6129916e47ecedd67bdb758
Author: David Gibson <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/ppc/spapr_hcall.c
M target/ppc/cpu.h
M target/ppc/machine.c
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Eliminate htab_base and htab_mask variables
CPUPPCState includes fields htab_base and htab_mask which store the base
address (GPA) and size (as a mask) of the guest's hashed page table (HPT).
These are set when the SDR1 register is updated.
Keeping these in sync with the SDR1 is actually a little bit fiddly, and
probably not useful for performance, since keeping them expands the size of
CPUPPCState. It also makes some upcoming changes harder to implement.
This patch removes these fields, in favour of calculating them directly
from the SDR1 contents when necessary.
This does make a change to the behaviour of attempting to write a bad value
(invalid HPT size) to the SDR1 with an mtspr instruction. Previously, the
bad value would be stored in SDR1 and could be retrieved with a later
mfspr, but the HPT size as used by the softmmu would be, clamped to the
allowed values. Now, writing a bad value is treated as a no-op. An error
message is printed in both new and old versions.
I'm not sure which behaviour, if either, matches real hardware. I don't
think it matters that much, since it's pretty clear that if an OS writes
a bad value to SDR1, it's not going to boot.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: e57ca75ce3b2bd33102573a8c0555d62e1bcfceb
https://github.com/qemu/qemu/commit/e57ca75ce3b2bd33102573a8c0555d62e1bcfceb
Author: David Gibson <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_hcall.c
M target/ppc/cpu.h
M target/ppc/kvm.c
M target/ppc/machine.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Manage external HPT via virtual hypervisor
The pseries machine type implements the behaviour of a PAPR compliant
hypervisor, without actually executing such a hypervisor on the virtual
CPU. To do this we need some hooks in the CPU code to make hypervisor
facilities get redirected to the machine instead of emulated internally.
For hypercalls this is managed through the cpu->vhyp field, which points
to a QOM interface with a method implementing the hypercall.
For the hashed page table (HPT) - also a hypervisor resource - we use an
older hack. CPUPPCState has an 'external_htab' field which when non-NULL
indicates that the HPT is stored in qemu memory, rather than within the
guest's address space.
For consistency - and to make some future extensions easier - this merges
the external HPT mechanism into the vhyp mechanism. Methods are added
to vhyp for the basic operations the core hash MMU code needs: map_hptes()
and unmap_hptes() for reading the HPT, store_hpte() for updating it and
hpt_mask() to retrieve its size.
To match this, the pseries machine now sets these vhyp fields in its
existing vhyp class, rather than reaching into the cpu object to set the
external_htab field.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Suraj Jitindar Singh <address@hidden>
Commit: 8d63351f9f99412fd2b99e2f5a8be2bc87d5670e
https://github.com/qemu/qemu/commit/8d63351f9f99412fd2b99e2f5a8be2bc87d5670e
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Remove the function ppc_hash64_set_sdr1()
The function ppc_hash64_set_sdr1 basically checked the htabsize and set an
error if it was too big, otherwise it just stored the value in SPR_SDR1.
Given that the only function which calls ppc_hash64_set_sdr1() is
ppc_store_sdr1(), why not handle the checking in ppc_store_sdr1() to avoid
the extra function call. Note that ppc_store_sdr1() already stores the
value in SPR_SDR1 anyway, so we were doing it twice.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
[dwg: Remove unnecessary error temporary]
Signed-off-by: David Gibson <address@hidden>
Commit: e78308fd3959c2694c8c366efdccacdd11997ac8
https://github.com/qemu/qemu/commit/e78308fd3959c2694c8c366efdccacdd11997ac8
Author: David Gibson <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/mmu-hash64.h
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Correct SDR1 masking
SDR_64_HTABORG, which indicates the bits of the SDR1 register to use for
the base of a 64-bit machine's hashed page table (HPT) isn't correct. It
includes the top 46 bits of the register, but in fact the top 4 bits must
be zero (according to the ISA v2.07). No actual implementation has
supported close to 2^60 bytes of physical address space, so it's kind of
irrelevant, but we might as well correct this.
In addition, although we checked for bad size values in SDR1, we never
reported an error if entirely invalid bits were set there. Add this check
to ppc_store_sdr1().
Reported-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: dd09c36159858c66ab6e47c688e4177dd3912bf0
https://github.com/qemu/qemu/commit/dd09c36159858c66ab6e47c688e4177dd3912bf0
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/cpu.c
M target/ppc/cpu.h
M target/ppc/translate.c
M target/ppc/translate_init.c
Log Message:
-----------
target/ppc: support for 32-bit carry and overflow
POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
and corresponding defines.
Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
is updated.
Arithmetic instructions:
* Addition and Substractions:
addic, addic., subfic, addc, subfc, adde, subfe, addme, subfme,
addze, and subfze always updates CA and CA32.
=> CA reflects the carry out of bit 0 in 64-bit mode and out of
bit 32 in 32-bit mode.
=> CA32 reflects the carry out of bit 32 independent of the
mode.
=> SO and OV reflects overflow of the 64-bit result in 64-bit
mode and overflow of the low-order 32-bit result in 32-bit
mode
=> OV32 reflects overflow of the low-order 32-bit independent of
the mode
* Multiply Low and Divide:
For mulld, divd, divde, divdu and divdeu: SO, OV, and OV32 bits
reflects overflow of the 64-bit result
For mullw, divw, divwe, divwu and divweu: SO, OV, and OV32 bits
reflects overflow of the 32-bit result
* Negate with OE=1 (nego)
For 64-bit mode if the register RA contains
0x8000_0000_0000_0000, OV and OV32 are set to 1.
For 32-bit mode if the register RA contains 0x8000_0000, OV and
OV32 are set to 1.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6b10d008a0c779e1226d197dfb9ba796559c1381
https://github.com/qemu/qemu/commit/6b10d008a0c779e1226d197dfb9ba796559c1381
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: update ca32 in arithmetic add
Adds routine to compute ca32 - gen_op_arith_compute_ca32
For 64-bit mode use the compute ca32 routine. While for 32-bit mode, CA
and CA32 will have same value.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 33903d0aa4191cbe7cd9e3b9019e11a2bb97aa14
https://github.com/qemu/qemu/commit/33903d0aa4191cbe7cd9e3b9019e11a2bb97aa14
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: update ca32 in arithmetic substract
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: dc0ad84449a4e2f28d2cc055998cb10c1a4d89a9
https://github.com/qemu/qemu/commit/dc0ad84449a4e2f28d2cc055998cb10c1a4d89a9
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: update overflow flags for add/sub
* SO and OV reflects overflow of the 64-bit result in 64-bit mode and
overflow of the low-order 32-bit result in 32-bit mode
* OV32 reflects overflow of the low-order 32-bit independent of the mode
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1480d71cbe811d453b393e3b342f102535fe1202
https://github.com/qemu/qemu/commit/1480d71cbe811d453b393e3b342f102535fe1202
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: use tcg ops for neg instruction
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 61aa9a697a1ec9b102e86cb7ea96876e6f20afe3
https://github.com/qemu/qemu/commit/61aa9a697a1ec9b102e86cb7ea96876e6f20afe3
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: add ov32 flag for multiply low insns
For Multiply Word:
SO, OV, and OV32 bits reflects overflow of the 32-bit result
For Multiply DoubleWord:
SO, OV, and OV32 bits reflects overflow of the 64-bit result
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c44027ffb91e7eb335f5a4d418906460044796b9
https://github.com/qemu/qemu/commit/c44027ffb91e7eb335f5a4d418906460044796b9
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: add ov32 flag in divide operations
Add helper_div_compute_ov() in the int_helper for updating the overflow
flags.
For Divide Word:
SO, OV, and OV32 bits reflects overflow of the 32-bit result
For Divide DoubleWord:
SO, OV, and OV32 bits reflects overflow of the 64-bit result
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b63d043418f76229a3637842cc1777280b695df1
https://github.com/qemu/qemu/commit/b63d043418f76229a3637842cc1777280b695df1
Author: Nikunj A Dadhania <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: add mcrxrx instruction
mcrxrx: Move to CR from XER Extended
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a8eeafda1930f49e2080e66b7a5ef493564838d1
https://github.com/qemu/qemu/commit/a8eeafda1930f49e2080e66b7a5ef493564838d1
Author: Greg Kurz <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/pci/pci.c
M hw/ppc/spapr_pci.c
M include/hw/pci/pci.h
Log Message:
-----------
spapr/pci: populate PCI DT in reverse order
Since commit 1d2d974244c6 "spapr_pci: enumerate and add PCI device tree", QEMU
populates the PCI device tree in the opposite order compared to SLOF.
Before 1d2d974244c6:
Populating /address@hidden
00 0000 (D) : 1af4 1000 virtio [ net ]
00 0800 (D) : 1af4 1001 virtio [ block ]
00 1000 (D) : 1af4 1009 virtio [ network ]
Populating /address@hidden/address@hidden
7e5294b8 : /address@hidden
7e52b998 : |-- address@hidden
7e52c0c8 : |-- address@hidden
7e52c7e8 : +-- address@hidden ok
Since 1d2d974244c6:
Populating /address@hidden
00 1000 (D) : 1af4 1009 virtio [ network ]
Populating /address@hidden/address@hidden
00 0800 (D) : 1af4 1001 virtio [ block ]
00 0000 (D) : 1af4 1000 virtio [ net ]
7e5e8118 : /address@hidden
7e5ea6a0 : |-- address@hidden
7e5eadb8 : |-- address@hidden
7e5eb4d8 : +-- address@hidden ok
This behaviour change is not actually a bug since no assumptions should be
made on DT ordering. But it has no real justification either, other than
being the consequence of the way fdt_add_subnode() inserts new elements
to the front of the FDT rather than adding them to the tail.
This patch reverts to the historical SLOF ordering by walking PCI devices
in reverse order. This reconciles pseries with x86 machine types behavior.
It is expected to make things easier when porting existing applications to
power.
Signed-off-by: Greg Kurz <address@hidden>
Tested-by: Thomas Huth <address@hidden>
Reviewed-by: Nikunj A Dadhania <address@hidden>
(slight update to the changelog)
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 738d5db8240a226ed370b84bf5f5775437bf1158
https://github.com/qemu/qemu/commit/738d5db8240a226ed370b84bf5f5775437bf1158
Author: David Gibson <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
xics: XICS should not be a SysBusDevice
Currently xics - the component of the IBM POWER interrupt controller
representing the overall interrupt fabric / architecture is
represented as a descendent of SysBusDevice. However, this is not
really correct - the xics presents nothing in MMIO space so it should
be an "unattached" device in the current QOM model.
Since this device will always be created by the machine type, not created
specifically from the command line, and because it has no migrated state
it should be safe to move it around the device composition tree.
Therefore this patch changes it to a descendent of TYPE_DEVICE, and
makes it an unattached device. So that its reset handler still gets
called correctly, we add a qdev_set_parent_bus() to attach it to
sysbus. It's not really clear that's correct (instead of using
register_reset()) but it appears to a common technique.
Signed-off-by: David Gibson <address@hidden>
[clg corrected problems with reset]
Signed-off-by: Cédric Le Goater <address@hidden>
[dwg folded together and updated commit message]
Signed-off-by: David Gibson <address@hidden>
Commit: 4e4169f7a22a47f1b03457390e105abcf8ebfcc2
https://github.com/qemu/qemu/commit/4e4169f7a22a47f1b03457390e105abcf8ebfcc2
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: remove set_nr_irqs() handler from XICSStateClass
Today, the ICS (Interrupt Controller Source) object is created and
realized by the init and realize routines of the XICS object, but some
of the parameters are only known at the machine level.
These parameters are passed from the sPAPR machine to the ICS object
in a rather convoluted way using property handlers and a class handler
of the XICS object. The number of irqs required to allocate the IRQ
state objects in the ICS realize routine is one of them.
Let's simplify the process by creating the ICS object along with the
XICS object at the machine level and link the ICS into the XICS list
of ICSs at this level also. In the sPAPR machine, there is only a
single ICS but that will change with the PowerNV machine.
Also, QOMify the creation of the objects and get rid of the
superfluous code.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 817bb6a4467366b6d1ecbb13a78450f91efd16bf
https://github.com/qemu/qemu/commit/817bb6a4467366b6d1ecbb13a78450f91efd16bf
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: remove set_nr_servers() handler from XICSStateClass
Today, the ICP (Interrupt Controller Presenter) objects are created by
the 'nr_servers' property handler of the XICS object and a class
handler. They are realized in the XICS object realize routine.
Let's simplify the process by creating the ICP objects along with the
XICS object at the machine level.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 681bfaded64537a408c5f6107dfe9969d6800861
https://github.com/qemu/qemu/commit/681bfaded64537a408c5f6107dfe9969d6800861
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M include/hw/ppc/spapr.h
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: store the ICS object under the sPAPR machine
A list of ICS objects was introduced under the XICS object for the
PowerNV machine but, for the sPAPR machine, it brings extra complexity
as there is only a single ICS. To simplify the code, let's add the ICS
pointer under the sPAPR machine and try to reduce the use of this list
where possible.
Also, change the xics_spapr_*() routines to use an ICS object instead
of an XICSState and change their name to reflect that these are
specific to the sPAPR ICS object.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b9038e7806dfe1e522fd7f8dff6a7502bd95a541
https://github.com/qemu/qemu/commit/b9038e7806dfe1e522fd7f8dff6a7502bd95a541
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
Log Message:
-----------
ppc/xics: add an InterruptStatsProvider interface to ICS and ICP objects
This is, again, to reduce the use of the list of ICS objects. Let's
make each individual ICS and ICP object an InterruptStatsProvider and
remove this same interface from XICSState.
The InterruptStatsProvider will be moved at the machine level after
the XICS cleanups are completed.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 51b180051e366c69b018af05c412b72282294d61
https://github.com/qemu/qemu/commit/51b180051e366c69b018af05c412b72282294d61
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: introduce a XICSFabric QOM interface to handle ICSs
This interface provides two simple handlers. One is to get an ICS
(Interrupt Source Controller) object from an irq number and a second
to resend the irqs when needed.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7844e12b287c01f5ebf242d6b69759bf067b4319
https://github.com/qemu/qemu/commit/7844e12b287c01f5ebf242d6b69759bf067b4319
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: use the QOM interface under the sPAPR machine
Add 'ics_get' and 'ics_resend' handlers to the sPAPR machine. These
are relatively simple for a single ICS.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f7759e4331ed04b2128af36efd395e55e3076406
https://github.com/qemu/qemu/commit/f7759e4331ed04b2128af36efd395e55e3076406
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_pci.c
M include/hw/pci-host/spapr.h
M include/hw/ppc/spapr_vio.h
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: use the QOM interface to get irqs
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2cd908d0add803886c310084145fecc93f080a63
https://github.com/qemu/qemu/commit/2cd908d0add803886c310084145fecc93f080a63
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: use the QOM interface to resend irqs
Also change the ICPState 'xics' backlink to be a XICSFabric, this
removes the need of using qdev_get_machine() to get the QOM interface
in some of the routines.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: be1fe35199e29bd662b9c7e36c97ccb7122f3fee
https://github.com/qemu/qemu/commit/be1fe35199e29bd662b9c7e36c97ccb7122f3fee
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: remove xics_find_source()
It is not used anymore now that we have the QOM interface for XICS.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c79b2fdd7bfc51de5f93c7008f7ed6a262389ed6
https://github.com/qemu/qemu/commit/c79b2fdd7bfc51de5f93c7008f7ed6a262389ed6
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
Log Message:
-----------
ppc/xics: register the reset handler of ICS objects
The reset of the ICS objects is currently handled by XICS but this can
be done for each individual ICS. This also reduces the use of the XICS
list of ICS.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d114a662253b4b9254f38449d9a7ef3b4b26480e
https://github.com/qemu/qemu/commit/d114a662253b4b9254f38449d9a7ef3b4b26480e
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: remove the XICS list of ICS
This is not used anymore.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b2fc59aaf90f3a0b6e1976d27ce533b035a40b49
https://github.com/qemu/qemu/commit/b2fc59aaf90f3a0b6e1976d27ce533b035a40b49
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: extend the QOM interface to handle ICPs
Let's add two new handlers for ICPs. One is to get an ICP object from
a server number and a second is to resend the irqs when needed.
The icp_resend() handler is a temporary workaround needed by the
ics-simple post_load() handler. It will be removed when the post_load
portion can be done at the machine level.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 729f8a4f4876107fdc56a0b80414368ee89afcd1
https://github.com/qemu/qemu/commit/729f8a4f4876107fdc56a0b80414368ee89afcd1
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics_kvm.c
Log Message:
-----------
ppc/xics: move kernel_xics_fd out of KVMXICSState
The kernel ICP file descriptor is the only reason behind the
KVMXICSState class and it's in the way of more cleanups. Let's make it
a static for the moment and move forward.
If this is problem, we could use an attribute under the sPAPR machine
later on.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: bf50860d1b3652e480b4efef9856afa428c3d8d4
https://github.com/qemu/qemu/commit/bf50860d1b3652e480b4efef9856afa428c3d8d4
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: simplify the cpu_setup() handler
The cpu_setup() handler currently takes a 'XICSState *' argument to
grab the kernel ICP file descriptor. This interface can be simplified
by using the 'xics' backlink of the ICP object.
This change is also required by subsequent patches which makes use of
the QOM interface for XICS.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f023243432b397ace5345bd47d4dc62609241484
https://github.com/qemu/qemu/commit/f023243432b397ace5345bd47d4dc62609241484
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: move the cpu_setup() handler under the ICPState class
The cpu_setup() handler is currently under the XICSState class but it
really belongs under ICPState as it is setting up an individual vCPU.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b4f27d71e3c98c9c4590de40d478004b8482b277
https://github.com/qemu/qemu/commit/b4f27d71e3c98c9c4590de40d478004b8482b277
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: use the QOM interface to grab an ICP
Also introduce a xics_icp_get() helper to simplify the changes.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b0ec31290cbf0df4c9945370aeb921248995543d
https://github.com/qemu/qemu/commit/b0ec31290cbf0df4c9945370aeb921248995543d
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: simplify spapr_dt_xics() interface
spapr_dt_xics() only needs the number of servers to build the device
tree nodes. Let's change the routine interface to reflect that.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 20147f2fceaa8a89176e49e1941f741d12a3364c
https://github.com/qemu/qemu/commit/20147f2fceaa8a89176e49e1941f741d12a3364c
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
Log Message:
-----------
ppc/xics: register the reset handler of ICP objects
The reset of the ICP objects is currently handled by XICS but this can
be done for each individual ICP.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 852ad27e14325be69c1afa2bb940ba7dc2ba1a8f
https://github.com/qemu/qemu/commit/852ad27e14325be69c1afa2bb940ba7dc2ba1a8f
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: move the ICP array under the sPAPR machine
This is the last step to remove the XICSState abstraction and have the
machine hold all the objects related to interrupts : ICSs and ICPs.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2192a9303d43ee5e1b2b65f5ed9a93922bcdd1df
https://github.com/qemu/qemu/commit/2192a9303d43ee5e1b2b65f5ed9a93922bcdd1df
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: export the XICS init routines
There is nothing left related to the XICS object in the realize
functions of the KVMXICSState and XICSState class. So adapt the
interfaces to call these routines directly from the sPAPR machine init
sequence.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e6f7e110ee7096ce2b98fa2963f3ec5e68130ea5
https://github.com/qemu/qemu/commit/e6f7e110ee7096ce2b98fa2963f3ec5e68130ea5
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: remove the XICSState classes
The XICSState classes are not used anymore. They have now been fully
deprecated by the XICSFabric QOM interface. Do the cleanups.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a7ff1212e99ff072dfb8db62d5e6d8ce9f4b486c
https://github.com/qemu/qemu/commit/a7ff1212e99ff072dfb8db62d5e6d8ce9f4b486c
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: move ics-simple post_load under the machine
The ICS object uses a post_load() handler which is implicitly relying
on the fact that the internal state of the ICS and ICP objects has
been restored but this is not guaranteed. So, let's move the code
under the post_load() handler of the machine where we know the objects
have been fully restored.
The icp_resend() handler of the XICSFabric QOM interface is also
removed as it is now obsolete.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6449da4545d35ce207f23a1dcc6189291ecf1a5f
https://github.com/qemu/qemu/commit/6449da4545d35ce207f23a1dcc6189291ecf1a5f
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: move InterruptStatsProvider to the sPAPR machine
It provides a better monitor output of the ICP and ICS objects, else
the objects are printed out of order.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8e4fba203e56b8676d1092c9415cb72521efa584
https://github.com/qemu/qemu/commit/8e4fba203e56b8676d1092c9415cb72521efa584
Author: Cédric Le Goater <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_kvm.c
Log Message:
-----------
ppc/xics: rename 'ICPState *' variables to 'icp'
'ICPState *' variables are currently named 'ss'. This is confusing, so
let's give them an appropriate name: 'icp'.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 356bb70ed1a8a741413d55e3dbc5ccd02c53d794
https://github.com/qemu/qemu/commit/356bb70ed1a8a741413d55e3dbc5ccd02c53d794
Author: Mike Nawrocki <address@hidden>
Date: 2017-03-01 (Wed, 01 Mar 2017)
Changed paths:
M target/ppc/Makefile.objs
M target/ppc/arch_dump.c
M target/ppc/cpu.h
M target/ppc/translate_init.c
Log Message:
-----------
Add PowerPC 32-bit guest memory dump support
This patch extends support for the `dump-guest-memory` command to the
32-bit PowerPC architecture. It relies on the assumption that a 64-bit
guest will not dump a 32-bit core file (and vice versa).
[dwg: I suspect this patch won't cover all cases, in particular a
32-bit machine type on a 64-bit qemu build. However, it does strictly
more than what we had before, so might as well apply as a starting
point]
Signed-off-by: Mike Nawrocki <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ab711e216b8a4c663ab89f50f2c6f10e8a4f8a54
https://github.com/qemu/qemu/commit/ab711e216b8a4c663ab89f50f2c6f10e8a4f8a54
Author: Peter Maydell <address@hidden>
Date: 2017-03-02 (Thu, 02 Mar 2017)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/pci/pci.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M include/hw/pci-host/spapr.h
M include/hw/pci/pci.h
M include/hw/pci/pci_ids.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_vio.h
M include/hw/ppc/xics.h
M target/ppc/Makefile.objs
M target/ppc/arch_dump.c
A target/ppc/cpu.c
M target/ppc/cpu.h
M target/ppc/int_helper.c
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/machine.c
M target/ppc/misc_helper.c
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/mmu_helper.c
M target/ppc/translate.c
M target/ppc/translate_init.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170301' into
staging
ppc patch queue for 2017-03-01
I was hoping to get this pull request squeezed in before the soft
freeze, but I ran into some difficulties during testing. Everything
here was at least posted before the soft freeze, so I'm hoping we can
still merge it for 2.9.
The biggest things here are:
* Cleanups to handling of hashed page tables, that will make
adding support for the POWER9 MMU easier
* Cleanups to the XICS interrupt controller that will make
implementing the powernv machine easier
* TCG implementation of extended overflow and carry handling for
POWER9
It also includes:
* Increasing the CPU limit for pseries to 1024 vCPUs
* Generating proper OF node names in qemu (making hotplug and
coldplug logic closer together)
# gpg: Signature made Wed 01 Mar 2017 04:43:06 GMT
# gpg: using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.9-20170301: (50 commits)
Add PowerPC 32-bit guest memory dump support
ppc/xics: rename 'ICPState *' variables to 'icp'
ppc/xics: move InterruptStatsProvider to the sPAPR machine
ppc/xics: move ics-simple post_load under the machine
ppc/xics: remove the XICSState classes
ppc/xics: export the XICS init routines
ppc/xics: move the ICP array under the sPAPR machine
ppc/xics: register the reset handler of ICP objects
ppc/xics: simplify spapr_dt_xics() interface
ppc/xics: use the QOM interface to grab an ICP
ppc/xics: move the cpu_setup() handler under the ICPState class
ppc/xics: simplify the cpu_setup() handler
ppc/xics: move kernel_xics_fd out of KVMXICSState
ppc/xics: extend the QOM interface to handle ICPs
ppc/xics: remove the XICS list of ICS
ppc/xics: register the reset handler of ICS objects
ppc/xics: remove xics_find_source()
ppc/xics: use the QOM interface to resend irqs
ppc/xics: use the QOM interface to get irqs
ppc/xics: use the QOM interface under the sPAPR machine
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/4bc0d39a2fd0...ab711e216b8a
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