[Qemu-commits] [qemu/qemu] cb539f: target-mips: Don't stop on [d]mtc0 DESAVE/KScratch

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: cb539fd241900f51de7d21244f7a55422ad0d40a
      
https://github.com/qemu/qemu/commit/cb539fd241900f51de7d21244f7a55422ad0d40a
  Author: James Hogan <address@hidden>
  Date:   2017-08-02 (Wed, 02 Aug 2017)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target-mips: Don't stop on [d]mtc0 DESAVE/KScratch

Writing to the MIPS DESAVE register (and now the KScratch registers)
will stop translation, supposedly due to risk of execution mode
switches. However these registers are basically RW scratch registers
with no side effects so there is no risk of them triggering execution
mode changes.

Drop the bstate = BS_STOP for these registers for both mtc0 and dmtc0.

Fixes: 7a387fffce50 ("Add MIPS32R2 instructions, and generally straighten out 
the instruction decoding. This is also the first percent towards MIPS64 
support.")
Signed-off-by: James Hogan <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Yongbok Kim <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 9652ef24bfaf59ba179787503fdf7eae6e95475b
      
https://github.com/qemu/qemu/commit/9652ef24bfaf59ba179787503fdf7eae6e95475b
  Author: Aurelien Jarno <address@hidden>
  Date:   2017-08-02 (Wed, 02 Aug 2017)

  Changed paths:
    M hw/mips/mips_malta.c

  Log Message:
  -----------
  mips/malta: leave space for the bootmap after the initrd

Since commit 9768e2abf7 the initrd is loaded at the end of the low
memory to avoid clash for the kernel relocation when kaslr is used.

However this in turn conflicts with the bootmap memory that the kernel
tries to place after initrd, but in low memory. The bootmap spans the
whole usable physical address space. The machine can have at most 2GiB
of memory, 256MiB of low memory mapped at 0x00000000, and 1792MiB of
high memory mapped at 0x90000000. The biggest bootmap therefore
corresponds to the adresses 0x00000000 -> 0xffffffff, which at 1 bit
per 4kiB page corresponds to 128kiB in memory.

Therefore reserve 128kiB after the initrd.

Signed-off-by: Aurelien Jarno <address@hidden>
Tested-by: Yongbok Kim <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 6743334568933199927af4992a04bfb3c30610f5
      
https://github.com/qemu/qemu/commit/6743334568933199927af4992a04bfb3c30610f5
  Author: James Hogan <address@hidden>
  Date:   2017-08-02 (Wed, 02 Aug 2017)

  Changed paths:
    M target/mips/helper.c

  Log Message:
  -----------
  mips: Improve segment defs for KVM T&E guests

Improve the segment definitions used by get_physical_address() to yield
target_ulong types, e.g. 0xffffffff80000000 instead of 0x80000000. This
is in preparation for enabling emulation of MIPS KVM T&E segments in TCG
MIPS targets, which unlike KVM could potentially have 64-bit
target_ulong. In such a case the offset guest KSEG0 address ends up at
e.g. 0x000000008xxxxxxx instead of 0xffffffff8xxxxxxx.

This also allows the casts to int32_t that force sign extension to be
removed, which removes any confusion due to relational comparison of
unsigned (target_ulong) and signed (int32_t) types.

Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: d3d93c6c1eb0d94d2f203ac272629e6ebfc468a7
      
https://github.com/qemu/qemu/commit/d3d93c6c1eb0d94d2f203ac272629e6ebfc468a7
  Author: James Hogan <address@hidden>
  Date:   2017-08-02 (Wed, 02 Aug 2017)

  Changed paths:
    M hw/mips/addr.c
    M hw/mips/mips_malta.c
    M include/hw/mips/cpudevs.h
    M target/mips/helper.c
    M target/mips/translate.c

  Log Message:
  -----------
  mips: Add KVM T&E segment support for TCG

MIPS KVM trap & emulate guest kernels have a different segment layout
compared with traditional MIPS kernels, to allow both the user and
kernel code to run from the user address segment without repeatedly
trapping to KVM.

QEMU currently supports this layout only for KVM, but its sometimes
useful to be able to run these kernels in QEMU on a PC, so enable it for
TCG too.

This also paves the way for MIPS KVM VZ support (which uses the normal
virtual memory layout) by abstracting whether user mode kernel segments
are in use.

Suggested-by: Paolo Bonzini <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
[Yongbok Kim:
  minor change]
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 2d1847ec1ca47fe82f1d8122409cedffdd3925d5
      
https://github.com/qemu/qemu/commit/2d1847ec1ca47fe82f1d8122409cedffdd3925d5
  Author: Leon Alrae <address@hidden>
  Date:   2017-08-02 (Wed, 02 Aug 2017)

  Changed paths:
    M target/mips/op_helper.c

  Log Message:
  -----------
  target-mips: apply CP0.PageMask before writing into TLB entry

PFN0 and PFN1 have to be masked out with PageMask_Mask.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
[Yongbok Kim:
  Added commit message]
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: b74cddcbf6063f684725e3f8bca49a68e30cba71
      
https://github.com/qemu/qemu/commit/b74cddcbf6063f684725e3f8bca49a68e30cba71
  Author: James Hogan <address@hidden>
  Date:   2017-08-02 (Wed, 02 Aug 2017)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Use BS_EXCP where interrupts are expected

Commit e350d8ca3ac7 ("target/mips: optimize indirect branches") made
indirect branches able to directly find the next TB and jump straight to
it without breaking out of translated code and going around the main
execution loop. This breaks the assumption in target/mips/translate.c
that BS_STOP is sufficient to cause pending interrupts to be handled,
since interrupts are only checked in the main loop.

Fix a few of these assumptions by using gen_save_pc to update the saved
PC and using BS_EXCP instead of BS_STOP:

 - [D]MFC0 CP0_Count may trigger a timer interrupt which should be
   immediately handled.

 - [D]MTC0 CP0_Cause may trigger an interrupt (but in fact translation
   was only even being stopped in the DMTC0 case).

 - [D]MTC0 CP0_<any> when icount is used is assumed could potentially
   cause interrupts.

 - EI may trigger an interrupt which was pending. I specifically hit
   this case when running KVM nested in mipsel-softmmu. A timer
   interrupt while the 2nd guest was executing is caught by KVM which
   switches back to the normal Linux exception base and re-enables
   interrupts with EI. Since the above commit QEMU doesn't leave
   translated code until the nested KVM has already restored the KVM
   exception base and returned to the 2nd guest, at which point it is
   too late to check for pending interrupts and it gets stuck in an
   infinite loop of unhandled interrupts.

Something similar was needed for ARM in commit b29fd33db578
("target/arm: use DISAS_EXIT for eret handling").

Fixes: e350d8ca3ac7 ("target/mips: optimize indirect branches")
Signed-off-by: James Hogan <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: 51ca717b079dccae5b6cc9f45153f5044abd34f0
      
https://github.com/qemu/qemu/commit/51ca717b079dccae5b6cc9f45153f5044abd34f0
  Author: James Hogan <address@hidden>
  Date:   2017-08-02 (Wed, 02 Aug 2017)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Drop redundant gen_io_start/stop()

DMTC0 CP0_Cause does a redundant gen_io_start() and gen_io_end() pair,
even though this is done for all DMTC0 operations outside of the switch
statement. Remove these redundant calls.

Fixes: 5dc5d9f055c5 ("mips: more fixes to the MIPS interrupt glue logic")
Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: d673a68db6963e86536b125af464bb6ed03eba33
      
https://github.com/qemu/qemu/commit/d673a68db6963e86536b125af464bb6ed03eba33
  Author: James Hogan <address@hidden>
  Date:   2017-08-02 (Wed, 02 Aug 2017)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Fix RDHWR CC with icount

RDHWR CC reads the CPU timer like MFC0 CP0_Count, so with icount enabled
it must set can_do_io while it calls the helper to avoid the "Bad icount
read" error. It should also break out of the translation loop to ensure
that timer interrupts are immediately handled.

Fixes: 2e70f6efa8b9 ("Add instruction counter.")
Signed-off-by: James Hogan <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Yongbok Kim <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>


  Commit: c233a35d3d91af666aa95a6a3ba8244d4ce728c6
      
https://github.com/qemu/qemu/commit/c233a35d3d91af666aa95a6a3ba8244d4ce728c6
  Author: Peter Maydell <address@hidden>
  Date:   2017-08-04 (Fri, 04 Aug 2017)

  Changed paths:
    M hw/mips/addr.c
    M hw/mips/mips_malta.c
    M include/hw/mips/cpudevs.h
    M target/mips/helper.c
    M target/mips/op_helper.c
    M target/mips/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170803' into staging

MIPS patches 2017-08-03

Changes:
KVM T&E segment support for TCG
malta: leave space for the bootmap after the initrd
Apply CP0.PageMask before writing into TLB entry
Fix fallout from indirect branch optimisation

# gpg: Signature made Thu 03 Aug 2017 15:32:59 BST
# gpg:                using RSA key 0x2238EB86D5F797C2
# gpg: Good signature from "Yongbok Kim <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA  2B5C 2238 EB86 D5F7 97C2

* remotes/yongbok/tags/mips-20170803:
  target/mips: Fix RDHWR CC with icount
  target/mips: Drop redundant gen_io_start/stop()
  target/mips: Use BS_EXCP where interrupts are expected
  target-mips: apply CP0.PageMask before writing into TLB entry
  mips: Add KVM T&E segment support for TCG
  mips: Improve segment defs for KVM T&E guests
  mips/malta: leave space for the bootmap after the initrd
  target-mips: Don't stop on [d]mtc0 DESAVE/KScratch

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/8377e9f60959...c233a35d3d91