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[Qemu-commits] [qemu/qemu] c4a2e3: target/ppc: Use tcg_gen_lookup_and_go


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] c4a2e3: target/ppc: Use tcg_gen_lookup_and_goto_ptr
Date: Fri, 15 Dec 2017 04:37:33 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c4a2e3a9709aa7c84def7bc4bfbdcaf37ccf7527
      
https://github.com/qemu/qemu/commit/c4a2e3a9709aa7c84def7bc4bfbdcaf37ccf7527
  Author: Richard Henderson <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Use tcg_gen_lookup_and_goto_ptr

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Daniel Henrique Barboza <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e0f7110acaaa222591e5f025953934c70c5ae15f
      
https://github.com/qemu/qemu/commit/e0f7110acaaa222591e5f025953934c70c5ae15f
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/intc/xics_spapr.c

  Log Message:
  -----------
  ppc/xics: remove useless if condition

The previous code section uses a 'first < 0' test and returns. Therefore,
there is no need to test the 'first' variable against '>= 0' afterwards.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2b6154120cbd7f5514cefd3c6084d39922d26d88
      
https://github.com/qemu/qemu/commit/2b6154120cbd7f5514cefd3c6084d39922d26d88
  Author: David Gibson <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr.c
    M include/hw/compat.h

  Log Message:
  -----------
  spapr: Add pseries-2.12 machine type

While we're at it fix a couple of small errors in the 2.11 and 2.10 models
(they didn't have any real effect, but don't quite match the template).

Signed-off-by: David Gibson <address@hidden>


  Commit: 94ad93bd976841c26af75322301f5aad925114d6
      
https://github.com/qemu/qemu/commit/94ad93bd976841c26af75322301f5aad925114d6
  Author: Greg Kurz <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M include/hw/ppc/spapr_cpu_core.h

  Log Message:
  -----------
  spapr_cpu_core: instantiate CPUs separately

The current code assumes that only the CPU core object holds a
reference on each individual CPU object, and happily frees their
allocated memory when the core is unrealized. This is dangerous
as some other code can legitimely keep a pointer to a CPU if it
calls object_ref(), but it would end up with a dangling pointer.

Let's allocate all CPUs with object_new() and let QOM free them
when their reference count reaches zero. This greatly simplify the
code as we don't have to fiddle with the instance size anymore.

Signed-off-by: Greg Kurz <address@hidden>
Acked-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e75ce32a75ba2fe78579882cfa06590edec2cd4a
      
https://github.com/qemu/qemu/commit/e75ce32a75ba2fe78579882cfa06590edec2cd4a
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/e500.c

  Log Message:
  -----------
  e500: name openpic and pci host bridge

Signed-off-by: Michael Davidsaver <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5d8424dbd3e8335ea3d57f64eaa603c8fc80706f
      
https://github.com/qemu/qemu/commit/5d8424dbd3e8335ea3d57f64eaa603c8fc80706f
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/nvram/Makefile.objs
    A hw/nvram/eeprom_at24c.c

  Log Message:
  -----------
  nvram: add AT24Cx i2c eeprom

Signed-off-by: Michael Davidsaver <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 403aacdb44219fcdb198e0293288a818b6cccc5d
      
https://github.com/qemu/qemu/commit/403aacdb44219fcdb198e0293288a818b6cccc5d
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M target/ppc/cpu-qom.h
    M target/ppc/translate_init.c

  Log Message:
  -----------
  pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass

and use the value to define precisely the default value of the LPCR in
the helper routine cpu_ppc_set_papr()

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: df592270447317d70c7f6ab204bbab27db1dee21
      
https://github.com/qemu/qemu/commit/df592270447317d70c7f6ab204bbab27db1dee21
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/intc/openpic.c

  Log Message:
  -----------
  openpic: debug w/ info_report()

Replace *printf() with *_report().
Remove trailing new lines.

Signed-off-by: Michael Davidsaver <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 67113c03423a23e60915574275aed7d60e9f85e1
      
https://github.com/qemu/qemu/commit/67113c03423a23e60915574275aed7d60e9f85e1
  Author: Michael Davidsaver <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/pci-host/ppce500.c

  Log Message:
  -----------
  e500: fix pci host bridge class/type

Correct some confusion wrt. the PCI facing
side of the PCI host bridge (not PCIe root complex).
The ref. manual for the mpc8533 (as well as
mpc8540 and mpc8540) give the class code as
PCI_CLASS_PROCESSOR_POWERPC.
While the PCI_HEADER_TYPE field is oddly omitted,
the tables in the "PCI Configuration Header"
section shows a type 0 layout using all 6 BAR
registers (as 2x 32, and 2x 64 bit regions)

So 997505065dc92e533debf5cb23012ba4e673d387
seems to be in error.  Although there was
perhaps some confusion as the mpc8533
has a separate PCIe root complex.
With PCIe, a root complex has PCI_HEADER_TYPE=1.

Neither the PCI host bridge, nor the PCIe
root complex advertise class PCI_CLASS_BRIDGE_PCI.

This was confusing Linux guests, which try
to interpret the host bridge as a pci-pci
bridge, but get confused and re-enumerate
the bus when the primary/secondary/subordinate
bus registers don't have valid values.

Signed-off-by: Michael Davidsaver <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9a94ee5bb15793ef69692998ef57794a33074134
      
https://github.com/qemu/qemu/commit/9a94ee5bb15793ef69692998ef57794a33074134
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr_rtas.c
    M target/ppc/translate_init.c

  Log Message:
  -----------
  spapr/rtas: disable the decrementer interrupt when a CPU is unplugged

When a CPU is stopped with the 'stop-self' RTAS call, its state
'halted' is switched to 1 and, in this case, the MSR is not taken into
account anymore in the cpu_has_work() routine. Only the pending
hardware interrupts are checked with their LPCR:PECE* enablement bit.

If the DECR timer fires after 'stop-self' is called and before the CPU
'stop' state is reached, the nearly-dead CPU will have some work to do
and the guest will crash. This case happens very frequently with the
not yet upstream P9 XIVE exploitation mode. In XICS mode, the DECR is
occasionally fired but after 'stop' state, so no work is to be done
and the guest survives.

I suspect there is a race between the QEMU mainloop triggering the
timers and the TCG CPU thread but I could not quite identify the root
cause. To be safe, let's disable in the LPCR all the exceptions which
can cause an exit while the CPU is in power-saving mode and reenable
them when the CPU is started.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d6322252b3210b663e303746f151abbae7d0b6db
      
https://github.com/qemu/qemu/commit/d6322252b3210b663e303746f151abbae7d0b6db
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  spapr/rtas: fix reboot of a a SMP TCG guest

Just like for hot unplug CPUs, when a guest is rebooted, the secondary
CPUs can be awaken by the decrementer and start entering SLOF at the
same time the boot CPU is.

To be safe, let's disable on the secondaries all the exceptions which
can cause an exit while the CPU is in power-saving mode.

Based on previous work from Nikunj A Dadhania <address@hidden>

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3fe4f0fc8530e9411819f02accf2d17c128061b0
      
https://github.com/qemu/qemu/commit/3fe4f0fc8530e9411819f02accf2d17c128061b0
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr_rtas.c

  Log Message:
  -----------
  spapr/rtas: do not reset the MSR in stop-self command

When a CPU is stopped with the 'stop-self' RTAS call, its state
'halted' is switched to 1 and, in this case, the MSR is not taken into
account anymore in the cpu_has_work() routine. Only the pending
hardware interrupts are checked with their LPCR:PECE* enablement bit.

The CPU is now also protected from the decrementer interrupt by the
LPCR:PECE* bits which are disabled in the 'stop-self' RTAS
call. Reseting the MSR is pointless.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4f7a47beebd6d37861d08c81941be1b33a0ae627
      
https://github.com/qemu/qemu/commit/4f7a47beebd6d37861d08c81941be1b33a0ae627
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/intc/xics.c
    M hw/ppc/pnv_core.c
    M hw/ppc/spapr_cpu_core.c
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  ppc/xics: introduce an icp_create() helper

The sPAPR and the PowerNV core objects create the interrupt presenter
object of the CPUs in a very similar way. Let's provide a common
routine in which we use the presenter 'type' as a child identifier.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ed0c37eedfdb953d61d1e0a41439cd404e914d9d
      
https://github.com/qemu/qemu/commit/ed0c37eedfdb953d61d1e0a41439cd404e914d9d
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/intc/xics.c
    M hw/ppc/pnv_core.c
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  ppc/xics: assign of the CPU 'intc' pointer under the core

The 'intc' pointer of the CPU references the interrupt presenter in
the XICS interrupt mode. When the XIVE interrupt mode is available and
activated, the machine will need to reassign this pointer to reflect
the change.

Moving this assignment under the realize routine of the CPU will ease
the process when the interrupt mode is toggled.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 60c6823b9bce6789f1ad95bca233fc490161b279
      
https://github.com/qemu/qemu/commit/60c6823b9bce6789f1ad95bca233fc490161b279
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/intc/trace-events
    M hw/intc/xics_spapr.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M hw/ppc/trace-events
    M include/hw/ppc/spapr.h
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  spapr: move the IRQ allocation routines under the machine

Also change the prototype to use a sPAPRMachineState and prefix them
with spapr_irq_. It will let us synchronise the IRQ allocation with
the XIVE interrupt mode when available.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9e7dc5fc2e9d87a5492099de72800347e944e4ea
      
https://github.com/qemu/qemu/commit/9e7dc5fc2e9d87a5492099de72800347e944e4ea
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: introduce a spapr_irq_set_lsi() helper

It will make synchronisation easier with the XIVE interrupt mode when
available. The 'irq' parameter refers to the global IRQ number space.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7718375584a0214c951668a6e92896aaed88b289
      
https://github.com/qemu/qemu/commit/7718375584a0214c951668a6e92896aaed88b289
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/intc/xics.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_vio.h
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  spapr: introduce a spapr_qirq() helper

xics_get_qirq() is only used by the sPAPR machine. Let's move it there
and change its name to reflect its scope. It will be useful for XIVE
support which will use its own set of qirqs.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f47bd1c839d57c12207a28421a9df718fbf476ba
      
https://github.com/qemu/qemu/commit/f47bd1c839d57c12207a28421a9df718fbf476ba
  Author: Igor Mammedov <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/mem/pc-dimm.c
    M hw/ppc/spapr.c
    M include/sysemu/numa.h
    M numa.c

  Log Message:
  -----------
  spapr: replace numa_get_node() with lookup in pc-dimm list

SPAPR is the last user of numa_get_node() and a bunch of
supporting code to maintain numa_info[x].addr list.

Get LMB node id from pc-dimm list, which allows to
remove ~80LOC maintaining dynamic address range
lookup list.

It also removes pc-dimm dependency on numa_[un]set_mem_node_id()
and makes pc-dimms a sole source of information about which
node it belongs to and removes duplicate data from global
numa_info.

Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: bb2d8ab6369abc8e90a9f7e2e8f154fea752bdaf
      
https://github.com/qemu/qemu/commit/bb2d8ab6369abc8e90a9f7e2e8f154fea752bdaf
  Author: Greg Kurz <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr: fix LSI interrupt specifiers in the device tree

LoPAPR 1.1 B.6.9.1.2 describes the "#interrupt-cells" property of the
PowerPC External Interrupt Source Controller node as follows:

“#interrupt-cells”

  Standard property name to define the number of cells in an interrupt-
  specifier within an interrupt domain.

  prop-encoded-array: An integer, encoded as with encode-int, that denotes
  the number of cells required to represent an interrupt specifier in its
  child nodes.

  The value of this property for the PowerPC External Interrupt option shall
  be 2. Thus all interrupt specifiers (as used in the standard “interrupts”
  property) shall consist of two cells, each containing an integer encoded
  as with encode-int. The first integer represents the interrupt number the
  second integer is the trigger code: 0 for edge triggered, 1 for level
  triggered.

This patch fixes the interrupt specifiers in the "interrupt-map" property
of the PHB node, that were setting the second cell to 8 (confusion with
IRQ_TYPE_LEVEL_LOW ?) instead of 1.

VIO devices and RTAS event sources use the same format for interrupt
specifiers: while here, we introduce a common helper to handle the
encoding details.

Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
--
v3: - reference public LoPAPR instead of internal PAPR+ in changelog
    - change helper name to spapr_dt_xics_irq()

v2: - drop the erroneous changes to the "interrupts" prop in PCI device nodes
    - introduce a common helper to encode interrupt specifiers
Signed-off-by: David Gibson <address@hidden>


  Commit: 638f2caa01eb1ec2c4acf4f43798bea465a7eeb5
      
https://github.com/qemu/qemu/commit/638f2caa01eb1ec2c4acf4f43798bea465a7eeb5
  Author: Greg Kurz <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr_events.c

  Log Message:
  -----------
  spapr_events: drop bogus cell from "interrupt-ranges" property

According to LoPAPR 1.1 B.6.12, the "/event-sources" node has an "interrupt-
ranges" property, the format of which is described in B.6.9.1.2 as follows:

“interrupt-ranges”
 Standard property name that defines the interrupt number(s) and range(s)
 handled by this unit.

 prop-encoded-array: List of (int-number, range) specifications.

 Int-number is encoded as with encode-int.
 Range is encoded as with encode-int.

 The first entry in this list shall contain the int-number associated with
 the first “reg” property entry. The int-num-ber is the value representing
 the interrupt source as would appear in the PowerPC External Interrupt
 Architecture XISR. The range shall be the number of sequential interrupt
 numbers which this unit can generate.

There's no such thing as a cell count at the end of the array, like the
one introduced by commit ffbb1705a33d in QEMU 2.8. It doesn't seem it had
any impact on existing guests and I couldn't find any related workaround
in linux. So, let's just drop the bogus lines.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2a83f9976efa9a85e8ceb9d1035a68f25c321334
      
https://github.com/qemu/qemu/commit/2a83f9976efa9a85e8ceb9d1035a68f25c321334
  Author: Cédric Le Goater <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M target/ppc/cpu.h

  Log Message:
  -----------
  target/ppc: introduce the PPC_BIT() macro

and use them in a couple of obvious places. Other macros will be used
in the model of the XIVE interrupt controller.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: bcb5ce08cf3ddf69af87cc0fe750c3b564f1e6af
      
https://github.com/qemu/qemu/commit/bcb5ce08cf3ddf69af87cc0fe750c3b564f1e6af
  Author: David Gibson <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Rename machine init functions for clarity

Machine objects have two init functions - the generic QOM level
instance_init which should only do static object initialization, and
the Machine specific MachineClass::init which does the actual
construction of the machine.

In spapr the functions implementing these two have names -
ppc_machine_initfn() and ppc_spapr_init() - which don't correspond closely
to either of those.  To prevent people (read, me) from confusing which is
which, rename them spapr_instance_init() and spapr_machine_init() to
make it clearer which is which.

While we're there rename ppc_spapr_reset() to spapr_machine_reset() to
match.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Suraj Jitindar Singh <address@hidden>


  Commit: 4f441474c61f317de7927edfdb1d042b0b6f3882
      
https://github.com/qemu/qemu/commit/4f441474c61f317de7927edfdb1d042b0b6f3882
  Author: David Gibson <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Assume msi_nonbroken

We conditionally adjust part of the guest device tree based on the
global msi_nonbroken flag.  However, the main machine type code
initializes msi_nonbroken to true and there's nothing that would set
it to false again.

So replace the test with an assert().

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>


  Commit: 1481fe5fcfeb7fcf3c1ebb9d8c0432e3e0188ccf
      
https://github.com/qemu/qemu/commit/1481fe5fcfeb7fcf3c1ebb9d8c0432e3e0188ccf
  Author: Laurent Vivier <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: don't initialize PATB entry if max-cpu-compat < power9

if KVM is enabled and KVM capabilities MMU radix is available,
the partition table entry (patb_entry) for the radix mode is
initialized by default in ppc_spapr_reset().

It's a problem if we want to migrate the guest to a POWER8 host
while the kernel is not started to set the value to the one
expected for a POWER8 CPU.

The "-machine max-cpu-compat=power8" should allow to migrate
a POWER9 KVM host to a POWER8 KVM host, but because patb_entry
is set, the destination QEMU tries to enable radix mode on the
POWER8 host. This fails and cancels the migration:

    Process table config unsupported by the host
    error while loading state for instance 0x0 of device 'spapr'
    load of migration failed: Invalid argument

This patch doesn't set the PATB entry if the user provides
a CPU compatibility mode that doesn't support radix mode.

Signed-off-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 96a6298889d6de688bc076f5f223b73297f85462
      
https://github.com/qemu/qemu/commit/96a6298889d6de688bc076f5f223b73297f85462
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-15 (Fri, 15 Dec 2017)

  Changed paths:
    M hw/intc/openpic.c
    M hw/intc/trace-events
    M hw/intc/xics.c
    M hw/intc/xics_spapr.c
    M hw/mem/pc-dimm.c
    M hw/nvram/Makefile.objs
    A hw/nvram/eeprom_at24c.c
    M hw/pci-host/ppce500.c
    M hw/ppc/e500.c
    M hw/ppc/pnv_core.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/spapr_vio.c
    M hw/ppc/trace-events
    M include/hw/compat.h
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_cpu_core.h
    M include/hw/ppc/spapr_vio.h
    M include/hw/ppc/xics.h
    M include/sysemu/numa.h
    M numa.c
    M target/ppc/cpu-qom.h
    M target/ppc/cpu.h
    M target/ppc/translate.c
    M target/ppc/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20171215' 
into staging

ppc patch queue 2017-12-15

First pull request for qemu-2.12.  This has quite a bit of stuff
accumulated while 2.11 was finalizing.  Highlights are:

  * Some preliminary work towards implementing the "XIVE" POWER9
    interrupt controller
  * Some fixes for problems during reboot with MTTCG
  * A substantial TCG performance improvement via
    tcg_get_lookup_and_goto_ptr
  * Numerous assorted cleanups and bugfixes that weren't urgent enough
    for 2.11

# gpg: Signature made Fri 15 Dec 2017 03:14:12 GMT
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.12-20171215: (24 commits)
  spapr: don't initialize PATB entry if max-cpu-compat < power9
  spapr: Assume msi_nonbroken
  spapr: Rename machine init functions for clarity
  target/ppc: introduce the PPC_BIT() macro
  spapr_events: drop bogus cell from "interrupt-ranges" property
  spapr: fix LSI interrupt specifiers in the device tree
  spapr: replace numa_get_node() with lookup in pc-dimm list
  spapr: introduce a spapr_qirq() helper
  spapr: introduce a spapr_irq_set_lsi() helper
  spapr: move the IRQ allocation routines under the machine
  ppc/xics: assign of the CPU 'intc' pointer under the core
  ppc/xics: introduce an icp_create() helper
  spapr/rtas: do not reset the MSR in stop-self command
  spapr/rtas: fix reboot of a a SMP TCG guest
  spapr/rtas: disable the decrementer interrupt when a CPU is unplugged
  e500: fix pci host bridge class/type
  openpic: debug w/ info_report()
  pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass
  nvram: add AT24Cx i2c eeprom
  e500: name openpic and pci host bridge
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/1c3b51a796a8...96a6298889d6

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