[Qemu-commits] [qemu/qemu] 09a573: cuda: convert to use the shared mos6522 device

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 09a573474ba0bb83df8159d0f24c0f209734da33
      
https://github.com/qemu/qemu/commit/09a573474ba0bb83df8159d0f24c0f209734da33
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M hw/misc/macio/cuda.c
    M hw/ppc/mac.h

  Log Message:
  -----------
  cuda: convert to use the shared mos6522 device

Add the relevant hooks as required for the MacOS timer calibration and delayed
SR interrupt.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7092e84d42b1cfc2440b1dcf66cdae814fa112b3
      
https://github.com/qemu/qemu/commit/7092e84d42b1cfc2440b1dcf66cdae814fa112b3
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M hw/misc/macio/cuda.c
    M hw/misc/macio/macio.c
    M hw/ppc/mac.h
    A include/hw/misc/macio/cuda.h

  Log Message:
  -----------
  ppc: move CUDAState and other CUDA-related definitions into separate cuda.h 
file

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4b402e09e6aa40365a11ed0d258ac1e973d9725b
      
https://github.com/qemu/qemu/commit/4b402e09e6aa40365a11ed0d258ac1e973d9725b
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M Makefile.objs
    M hw/misc/macio/cuda.c
    A hw/misc/macio/trace-events

  Log Message:
  -----------
  cuda: convert to trace-events

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9478956794c11239b7c1c3ef9ce95c883bb839a3
      
https://github.com/qemu/qemu/commit/9478956794c11239b7c1c3ef9ce95c883bb839a3
  Author: Daniel Henrique Barboza <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M hw/ppc/spapr_hcall.c

  Log Message:
  -----------
  hw/ppc/spapr_hcall: set htab_shift after kvmppc_resize_hpt_commit

Newer kernels have a htab resize capability when adding or remove
memory. At these situations, the guest kernel might reallocate its
htab to a more suitable size based on the resulting memory.

However, we're not setting the new value back into the machine state
when a KVM guest resizes its htab. At first this doesn't seem harmful,
but when migrating or saving the guest state (via virsh managedsave,
for instance) this mismatch between the htab size of QEMU and the
kernel makes the guest hangs when trying to load its state.

Inside h_resize_hpt_commit, the hypercall that commits the hash page
resize changes, let's set spapr->htab_shift to the new value if we're
sure that kvmppc_resize_hpt_commit were successful.

While we're here, add a "not RADIX" sanity check as it is already done
in the related hypercall h_resize_hpt_prepare.

Fixes: https://github.com/open-power-host-os/qemu/issues/28
Reported-by: Satheesh Rajendran <address@hidden>
Signed-off-by: Daniel Henrique Barboza <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2cc75c32e6fcbc1a9732a6589c7dcacf295b5b84
      
https://github.com/qemu/qemu/commit/2cc75c32e6fcbc1a9732a6589c7dcacf295b5b84
  Author: Laurent Vivier <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M hw/char/escc.c
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c
    M hw/sparc/sun4m.c
    M include/hw/char/escc.h

  Log Message:
  -----------
  hw/char: remove legacy interface escc_init()

Move necessary stuff in escc.h and update type names.
Remove slavio_serial_ms_kbd_init().
Fix code style problems reported by checkpatch.pl
Update mac_newworld, mac_oldworld and sun4m to use directly the
QDEV interface.

Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8c5909c41916f25b47bfdc465059a926603c1319
      
https://github.com/qemu/qemu/commit/8c5909c41916f25b47bfdc465059a926603c1319
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M hw/ppc/spapr_caps.c

  Log Message:
  -----------
  ppc/spapr-caps: Change migration macro to take full spapr-cap name

Change the macro that generates the vmstate migration field and the needed
function for the spapr-caps to take the full spapr-cap name. This has
the benefit of meaning this instance will be picked up when greping
for the spapr-caps and making it more obvious what this macro is doing.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 72194664c8a16b67865eb95054f984dd169cfa86
      
https://github.com/qemu/qemu/commit/72194664c8a16b67865eb95054f984dd169cfa86
  Author: Greg Kurz <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: use spapr->vsmt to compute VCPU ids

Since the introduction of VSMT in 2.11, the spacing of VCPU ids
between cores is controllable through a machine property instead
of being only dictated by the SMT mode of the host:

    cpu->vcpu_id = (cc->core_id * spapr->vsmt / smp_threads) + i

Until recently, the machine code would try to change the SMT mode
of the host to be equal to VSMT or exit. This allowed the rest of
the code to assume that kvmppc_smt_threads() == spapr->vsmt is
always true.

Recent commit "8904e5a75005 spapr: Adjust default VSMT value for
better migration compatibility" relaxed the rule. If the VSMT
mode cannot be set in KVM for some reasons, but the requested
CPU topology is compatible with the current SMT mode, then we
let the guest run with  kvmppc_smt_threads() != spapr->vsmt.

This breaks quite a few places in the code, in particular when
calculating DRC indexes.

This is what happens on a POWER host with subcores-per-core=2 (ie,
supports up to SMT4) when passing the following topology:

    -smp threads=4,maxcpus=16 \
    -device host-spapr-cpu-core,core-id=4,id=core1 \
    -device host-spapr-cpu-core,core-id=8,id=core2

qemu-system-ppc64: warning: Failed to set KVM's VSMT mode to 8 (errno -22)

This is expected since KVM is limited to SMT4, but the guest is started
anyway because this topology can run on SMT4 even with a VSMT8 spacing.

But when we look at the DT, things get nastier:

cpus {
  ...
  ibm,drc-indexes = <0x4 0x10000000 0x10000004 0x10000008 0x1000000c>;

This means that we have the following association:

 CPU core device |     DRC    | VCPU id
-----------------+------------+---------
   boot core     | 0x10000000 | 0
   core1         | 0x10000004 | 4
   core2         | 0x10000008 | 8
   core3         | 0x1000000c | 12

But since the spacing of VCPU ids is 8, the DRC for core1 points to a
VCPU that doesn't exist, the DRC for core2 points to the first VCPU of
core1 and and so on...
   ...
   PowerPC,address@hidden {
          ...
          ibm,my-drc-index = <0x10000000>;
          ...
  };
   PowerPC,address@hidden {
          ...
          ibm,my-drc-index = <0x10000008>;
          ...
  };
   PowerPC,address@hidden {
          ...

No ibm,my-drc-index property for this core since 0x10000010 doesn't
exist in ibm,drc-indexes above.
           ...
  };
};

...

interrupt-controller {
  ...
  ibm,interrupt-server-ranges = <0x0 0x10>;

With a spacing of 8, the highest VCPU id for the given topology should be:
  16 * 8 / 4 = 32 and not 16
   ...
  linux,phandle = <0x7e7323b8>;
  interrupt-controller;
};

And CPU hot-plug/unplug is broken:

(qemu) device_del core1
pseries-hotplug-cpu: Cannot find CPU (drc index 10000004) to remove

(qemu) device_del core2
cpu 4 (hwid 8) Ready to die...
cpu 5 (hwid 9) Ready to die...
cpu 6 (hwid 10) Ready to die...
cpu 7 (hwid 11) Ready to die...

These are the VCPU ids of core1 actually

(qemu) device_add host-spapr-cpu-core,core-id=12,id=core3
(qemu) device_del core3
pseries-hotplug-cpu: Cannot find CPU (drc index 1000000c) to remove

This patches all the code in hw/ppc/spapr.c to assume the VSMT
spacing when manipulating VCPU ids.

Fixes: 8904e5a75005
Signed-off-by: Greg Kurz <address@hidden>

Signed-off-by: David Gibson <address@hidden>


  Commit: 648edb64751ea0e550f36302fa66f9f11e480824
      
https://github.com/qemu/qemu/commit/648edb64751ea0e550f36302fa66f9f11e480824
  Author: Greg Kurz <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr: move VCPU calculation to core machine code

The VCPU ids are currently computed and assigned to each individual
CPU threads in spapr_cpu_core_realize(). But the numbering logic
of VCPU ids is actually a machine-level concept, and many places
in hw/ppc/spapr.c also have to compute VCPU ids out of CPU indexes.

The current formula used in spapr_cpu_core_realize() is:

    vcpu_id = (cc->core_id * spapr->vsmt / smp_threads) + i

where:

    cc->core_id is a multiple of smp_threads
    cpu_index = cc->core_id + i
    0 <= i < smp_threads

So we have:

    cpu_index % smp_threads == i
    cc->core_id / smp_threads == cpu_index / smp_threads

hence:

    vcpu_id =
  (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;

This formula was used before VSMT at the time VCPU ids where computed
at the target emulation level. It has the advantage of being useable
to derive a VPCU id out of a CPU index only. It is fitted for all the
places where the machine code has to compute a VCPU id.

This patch introduces an accessor to set the VCPU id in a PowerPCCPU object
using the above formula. It is a first step to consolidate all the VCPU id
logic in a single place.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 14bb4486c819ea797a151b3e0fe53d6f5c7b3fc5
      
https://github.com/qemu/qemu/commit/14bb4486c819ea797a151b3e0fe53d6f5c7b3fc5
  Author: Greg Kurz <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr: rename spapr_vcpu_id() to spapr_get_vcpu_id()

The spapr_vcpu_id() function is an accessor actually. Let's rename it
for symmetry with the recently added spapr_set_vcpu_id() helper.

The motivation behind this is that a later patch will consolidate
the VCPU id formula in a function and spapr_vcpu_id looks like an
appropriate name.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5d0fb1508e2d279da74ef4a103e8def9b52c6304
      
https://github.com/qemu/qemu/commit/5d0fb1508e2d279da74ef4a103e8def9b52c6304
  Author: Greg Kurz <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: consolidate the VCPU id numbering logic in a single place

Several places in the code need to calculate a VCPU id:

    (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads
    (core_id / smp_threads) * spapr->vsmt (1 user)
    index * spapr->vsmt (2 users)

or guess that the VCPU id of a given VCPU is the first thread of a virtual
core:

    index % spapr->vsmt != 0

Even if the numbering logic isn't that complex, it is rather fragile to
have these assumptions open-coded in several places. FWIW this was
proved with recent issues related to VSMT.

This patch moves the VCPU id formula to a single function to be called
everywhere the code needs to compute one. It also adds an helper to
guess if a VCPU is the first thread of a VCORE.

Signed-off-by: Greg Kurz <address@hidden>
[dwg: Rename spapr_is_vcore() to spapr_is_thread0_in_vcore() for clarity]
Signed-off-by: David Gibson <address@hidden>


  Commit: b6bac4bc7016531405d117cfc1bf64145799e164
      
https://github.com/qemu/qemu/commit/b6bac4bc7016531405d117cfc1bf64145799e164
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M target/ppc/translate.c
    M target/ppc/translate/dfp-impl.inc.c
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: convert to DisasContextBase

A couple of notes:

- removed ctx->nip in favour of base->pc_next. Yes, it is annoying,
  but didn't want to waste its 4 bytes.

- ctx->singlestep_enabled does a lot more than
  base.singlestep_enabled; this confused me at first.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b0c2d5213a14f8b9d44096ee879a5d7f10fbc505
      
https://github.com/qemu/qemu/commit/b0c2d5213a14f8b9d44096ee879a5d7f10fbc505
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: convert to TranslatorOps

A few changes worth noting:

- Didn't migrate ctx->exception to DISAS_* since the exception field is
  in many cases architecturally relevant.

- Moved the cross-page check from the end of translate_insn to tb_start.

- Removed the exit(1) after a TCG temp leak; changed the fprintf there to
  qemu_log.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4f5b039d2bf9bb26b6e26a3dc65da36fe970cba9
      
https://github.com/qemu/qemu/commit/4f5b039d2bf9bb26b6e26a3dc65da36fe970cba9
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M hw/ppc/spapr_caps.c

  Log Message:
  -----------
  ppc/spapr-caps: Disallow setting workaround for spapr-cap-ibs

The spapr-cap cap-ibs can only have values broken or fixed as there is
no explicit workaround required. Currently setting the value workaround
for this cap will hit an assert if the guest makes the hcall
h_get_cpu_characteristics.

Report an error when attempting to apply the setting with a more helpful
error message.

Reported-by: Satheesh Rajendran <address@hidden>
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 58d5b22bbd505dc942d137d5d3da89ad9bc16c0a
      
https://github.com/qemu/qemu/commit/58d5b22bbd505dc942d137d5d3da89ad9bc16c0a
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    A hw/ppc/ppc440.h
    A hw/ppc/ppc440_uc.c
    M include/hw/pci/pcie_host.h

  Log Message:
  -----------
  ppc4xx: Add device models found in PPC440 core SoCs

These devices are found in newer SoCs based on 440 core e.g. the 460EX
(http://www.embeddeddeveloper.com/assets/processors/amcc/datasheets/
PP460EX_DS2063.pdf)

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d9c92ae335d99dd32c52fc7b075ef4820b4c6571
      
https://github.com/qemu/qemu/commit/d9c92ae335d99dd32c52fc7b075ef4820b4c6571
  Author: Peter Maydell <address@hidden>
  Date:   2018-02-16 (Fri, 16 Feb 2018)

  Changed paths:
    M Makefile.objs
    M hw/char/escc.c
    M hw/misc/macio/cuda.c
    M hw/misc/macio/macio.c
    A hw/misc/macio/trace-events
    M hw/ppc/mac.h
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c
    A hw/ppc/ppc440.h
    A hw/ppc/ppc440_uc.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_hcall.c
    M hw/sparc/sun4m.c
    M include/hw/char/escc.h
    A include/hw/misc/macio/cuda.h
    M include/hw/pci/pcie_host.h
    M include/hw/ppc/spapr.h
    M target/ppc/translate.c
    M target/ppc/translate/dfp-impl.inc.c
    M target/ppc/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180216' 
into staging

ppc patch queue 2018-02-16

Highlights of this batch:
  * Conversion to TranslatorOps (Emilio Cota)
  * Further bugfixes and cleanups to vcpu id allocation for pseries
    (Greg Kurz)
  * Another bugfix for HPT resizing (Daniel Henrique-Barboza)
  * Macintosh CUDA cleanups (Mark Cave-Ayland)
  * Further tweaks to Spectre/Meltdown mitigations (Suraj Singh)

# gpg: Signature made Fri 16 Feb 2018 10:00:02 GMT
# gpg:                using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.12-20180216:
  ppc4xx: Add device models found in PPC440 core SoCs
  ppc/spapr-caps: Disallow setting workaround for spapr-cap-ibs
  target/ppc: convert to TranslatorOps
  target/ppc: convert to DisasContextBase
  spapr: consolidate the VCPU id numbering logic in a single place
  spapr: rename spapr_vcpu_id() to spapr_get_vcpu_id()
  spapr: move VCPU calculation to core machine code
  spapr: use spapr->vsmt to compute VCPU ids
  ppc/spapr-caps: Change migration macro to take full spapr-cap name
  hw/char: remove legacy interface escc_init()
  hw/ppc/spapr_hcall: set htab_shift after kvmppc_resize_hpt_commit
  cuda: convert to trace-events
  ppc: move CUDAState and other CUDA-related definitions into separate cuda.h 
file
  cuda: convert to use the shared mos6522 device

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/648ba9159616...d9c92ae335d9