[Qemu-commits] [qemu/qemu] 4e5f0f: hw: register: Run post_write hook on reset

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 4e5f0fb72ee2a8872cec469fd9fe414711de3908
      
https://github.com/qemu/qemu/commit/4e5f0fb72ee2a8872cec469fd9fe414711de3908
  Author: Alistair Francis <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M hw/core/register.c
    M include/hw/register.h

  Log Message:
  -----------
  hw: register: Run post_write hook on reset

Ensure that the post write hook is called during reset. This allows us
to rely on the post write functions instead of having to call them from
the reset() function.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c4a94b8e3904cffedfbb959587ddce8643e45fd
      
https://github.com/qemu/qemu/commit/0c4a94b8e3904cffedfbb959587ddce8643e45fd
  Author: Francisco Iglesias <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Enable only two slaves when reading/writing with stripe

Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
chip selects are enabled (e.g reading/writing with stripe).

Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b8cc8503521282fe741e4d24ade9157210fdf3ba
      
https://github.com/qemu/qemu/commit/b8cc8503521282fe741e4d24ade9157210fdf3ba
  Author: Francisco Iglesias <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands

Use 8 dummy cycles (4 dummy bytes) with the QIOR/QIOR4 commands in legacy mode
for matching what is expected by Micron (Numonyx) flashes (the default target
flash type of the QSPI).

Signed-off-by: Francisco Iglesias <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 373b8ac794291c9a20198ac671728dbd74ac3771
      
https://github.com/qemu/qemu/commit/373b8ac794291c9a20198ac671728dbd74ac3771
  Author: Corey Minyard <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M hw/i2c/core.c
    M include/hw/i2c/i2c.h

  Log Message:
  -----------
  i2c: Fix some brace style issues

Signed-off-by: Corey Minyard <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Linus Walleij <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aa88d7ad28eafaa7ac187d5bbb0c46f987fac3a4
      
https://github.com/qemu/qemu/commit/aa88d7ad28eafaa7ac187d5bbb0c46f987fac3a4
  Author: Corey Minyard <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M hw/i2c/core.c
    M include/hw/i2c/i2c.h

  Log Message:
  -----------
  i2c: Move the bus class to i2c.h

Some devices need access to it.

Signed-off-by: Corey Minyard <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Linus Walleij <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 839a2b28d01290c96554be42c3faaa05c847c2e3
      
https://github.com/qemu/qemu/commit/839a2b28d01290c96554be42c3faaa05c847c2e3
  Author: Linus Walleij <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M hw/i2c/i2c-ddc.c

  Log Message:
  -----------
  hw/i2c-ddc: Do not fail writes

The tx function of the DDC I2C slave emulation was returning 1
on all writes resulting in NACK in the I2C bus. Changing it to
0 makes the DDC I2C work fine with bit-banged I2C such as the
versatile I2C.

I guess it was not affecting whatever I2C controller this was
used with until now, but with the Versatile I2C it surely
does not work.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Linus Walleij <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a643bd7749d41de2cfc54940636442ebc4f9e531
      
https://github.com/qemu/qemu/commit/a643bd7749d41de2cfc54940636442ebc4f9e531
  Author: Linus Walleij <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M hw/display/Makefile.objs
    A hw/display/sii9022.c
    M hw/display/trace-events

  Log Message:
  -----------
  hw/sii9022: Add support for Silicon Image SII9022

This adds support for emulating the Silicon Image SII9022 DVI/HDMI
bridge. It's not very clever right now, it just acknowledges
the switch into DDC I2C mode and back. Combining this with the
existing DDC I2C emulation gives the right behavior on the Versatile
Express emulation passing through the QEMU EDID to the emulated
platform.

Cc: Peter Maydell <address@hidden>
Signed-off-by: Linus Walleij <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: explictly reset ddc_req/ddc_skip_finish/ddc]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0b72476810a83de270194b1de65027e4be204779
      
https://github.com/qemu/qemu/commit/0b72476810a83de270194b1de65027e4be204779
  Author: Linus Walleij <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/vexpress.c

  Log Message:
  -----------
  arm/vexpress: Add proper display connector emulation

This adds the SiI9022 (and implicitly EDID I2C) device to the ARM
Versatile Express machine, and selects the two I2C devices necessary
in the arm-softmmu.mak configuration so everything will build
smoothly.

I am implementing proper handling of the graphics in the Linux
kernel and adding proper emulation of SiI9022 and EDID makes the
driver probe as nicely as before, retrieving the resolutions
supported by the "QEMU monitor" and overall just working nice.

Cc: Peter Maydell <address@hidden>
Signed-off-by: Linus Walleij <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 35737497008aeabce5dc381a41d3827bec486192
      
https://github.com/qemu/qemu/commit/35737497008aeabce5dc381a41d3827bec486192
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M include/exec/helper-head.h

  Log Message:
  -----------
  include/exec/helper-head.h: support f16 in helper calls

This allows us to explicitly pass float16 to helpers rather than
assuming uint32_t and dealing with the result. Of course they will be
passed in i32 sized registers by default.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6ad4d6187563f069fe5f11c3c1c9ccec1f69c2b7
      
https://github.com/qemu/qemu/commit/6ad4d6187563f069fe5f11c3c1c9ccec1f69c2b7
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm/cpu64: introduce ARM_V8_FP16 feature bit

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: postpone actually enabling feature until end of the
 patch series]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d0e69ea88f4e74212b29d9436143c5bcfd437757
      
https://github.com/qemu/qemu/commit/d0e69ea88f4e74212b29d9436143c5bcfd437757
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm/cpu.h: update comment for half-precision values

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d81ce0ef2c4f1052fcdef891a12499eca3084db7
      
https://github.com/qemu/qemu/commit/d81ce0ef2c4f1052fcdef891a12499eca3084db7
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm/cpu.h: add additional float_status flags

Half-precision flush to zero behaviour is controlled by a separate
FZ16 bit in the FPCR. To handle this we pass a pointer to
fp_status_fp16 when working on half-precision operations. The value of
the presented FPCR is calculated from an amalgam of the two when read.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9b04991686785e18b18a36d193b68f08f7c91648
      
https://github.com/qemu/qemu/commit/9b04991686785e18b18a36d193b68f08f7c91648
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm/helper: pass explicit fpst to set_rmode

As the rounding mode is now split between FP16 and the rest of
floating point we need to be explicit when tweaking it. Instead of
passing the CPU env we now pass the appropriate fpst pointer directly.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 807cdd504283c11addcd7ea95ba594bbddc86fe4
      
https://github.com/qemu/qemu/commit/807cdd504283c11addcd7ea95ba594bbddc86fe4
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)

This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3840d219b433507f04a685120ff770ce4e06c55d
      
https://github.com/qemu/qemu/commit/3840d219b433507f04a685120ff770ce4e06c55d
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: handle_3same_64 comment fix

We do implement all the opcodes.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 376e8d6cda985df31c8561db4b7ea365b6fe6f87
      
https://github.com/qemu/qemu/commit/376e8d6cda985df31c8561db4b7ea365b6fe6f87
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: initial decode for simd_three_reg_same_fp16

This is the initial decode skeleton for the Advanced SIMD three same
instruction group.

The fprintf is purely to aid debugging as the additional instructions
are added. It will be removed once the group is complete.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 372087348d561e7f4051d7b32609bda417092ddf
      
https://github.com/qemu/qemu/commit/372087348d561e7f4051d7b32609bda417092ddf
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to 
simd_three_reg_same_fp16

The fprintf is only there for debugging as the skeleton is added to,
it will be removed once the skeleton is complete.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d32adeae1a71a8e71374fa48d3d6ab0ad4c23e94
      
https://github.com/qemu/qemu/commit/d32adeae1a71a8e71374fa48d3d6ab0ad4c23e94
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16

These use the generic float16_compare functionality which in turn uses
the common float_compare code from the softfloat re-factor.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2deb992b767d28035fac3b374c7730494ff0b43d
      
https://github.com/qemu/qemu/commit/2deb992b767d28035fac3b374c7730494ff0b43d
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 026e2d6ef74000afb9049f46add4b94f594c8fb3
      
https://github.com/qemu/qemu/commit/026e2d6ef74000afb9049f46add4b94f594c8fb3
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M include/fpu/softfloat.h
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16

As some of the constants here will also be needed
elsewhere (specifically for the upcoming SVE support) we move them out
to softfloat.h.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7a2c6e618156674cf9eac8bf36e79f674fbf974e
      
https://github.com/qemu/qemu/commit/7a2c6e618156674cf9eac8bf36e79f674fbf974e
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16

This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5d265064cf30daaacce5a4ce9945fc573015fb5f
      
https://github.com/qemu/qemu/commit/5d265064cf30daaacce5a4ce9945fc573015fb5f
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed

The helpers use the new re-factored muladd support in SoftFloat for
the float16 work.

Signed-off-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6089030c7322d8f96b54fb9904e53b0f464bb8fe
      
https://github.com/qemu/qemu/commit/6089030c7322d8f96b54fb9904e53b0f464bb8fe
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 x2 ops for simd_indexed

A bunch of the vectorised bitwise operations just operate on larger
chunks at a time. We can do the same for the new half-precision
operations by introducing some TWOHALFOP helpers which work on each
half of a pair of half-precision operations at once.

Hopefully all this hoop jumping will get simpler once we have
generically vectorised helpers here.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5d432be6fd6efe37833ac82623c3abd35117b421
      
https://github.com/qemu/qemu/commit/5d432be6fd6efe37833ac82623c3abd35117b421
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: initial decode for simd_two_reg_misc_fp16

This actually covers two different sections of the encoding table:

   Advanced SIMD scalar two-register miscellaneous FP16
   Advanced SIMD two-register miscellaneous (FP16)

The difference between the two is covered by a combination of Q (bit
30) and S (bit 28). Notably the FRINTx instructions are only
available in the vector form.

This is just the decode skeleton which will be filled out by later
patches.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6109aea2d954891027acba64a13f1f1c7463cfac
      
https://github.com/qemu/qemu/commit/6109aea2d954891027acba64a13f1f1c7463cfac
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16

This adds the full range of half-precision floating point to integral
instructions.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2df581304193d70eaf0d22cf4cb4613f74b6e59b
      
https://github.com/qemu/qemu/commit/2df581304193d70eaf0d22cf4cb4613f74b6e59b
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16

This covers all the floating point convert operations.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7d4dd1a73a023f75c893623710e43743501b318e
      
https://github.com/qemu/qemu/commit/7d4dd1a73a023f75c893623710e43743501b318e
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16

I re-use the existing handle_2misc_fcmp_zero handler and tweak it
slightly to deal with the half-precision case.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 931931904cb56b9310a1a9c7f88adfce7d9bd82b
      
https://github.com/qemu/qemu/commit/931931904cb56b9310a1a9c7f88adfce7d9bd82b
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16

I've re-factored the handle_simd_intfp_conv helper to properly handle
half-precision as well as call plain conversion helpers when we are
not doing fixed point conversion.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 15f8a233c8c023dbc77b6fe6cd7c79eac9bee263
      
https://github.com/qemu/qemu/commit/15f8a233c8c023dbc77b6fe6cd7c79eac9bee263
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16

Neither of these operations alter the floating point status registers
so we can do a pure bitwise operation, either squashing any sign
bit (ABS) or inverting it (NEG).

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5eb70735af1c0b607bf2671a53aff3710cc1672f
      
https://github.com/qemu/qemu/commit/5eb70735af1c0b607bf2671a53aff3710cc1672f
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper.c
    M target/arm/helper.h

  Log Message:
  -----------
  arm/helper.c: re-factor recpe and add recepe_f16

It looks like the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final packing of the result.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fbd06e1e4b6566b4d727f9e553c819d034942f68
      
https://github.com/qemu/qemu/commit/fbd06e1e4b6566b4d727f9e553c819d034942f68
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FRECPE

Now we have added f16 during the re-factoring we can simply call the
helper.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 986950283837f697b35782b9ac3bc99fca614640
      
https://github.com/qemu/qemu/commit/986950283837f697b35782b9ac3bc99fca614640
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16

We go with the localised helper.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b96a54c7e5576bd35b7d00d37b7929d2892d8cac
      
https://github.com/qemu/qemu/commit/b96a54c7e5576bd35b7d00d37b7929d2892d8cac
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d719cbc7641991d16b891ffbbfc3a16a04e37b9a
      
https://github.com/qemu/qemu/commit/d719cbc7641991d16b891ffbbfc3a16a04e37b9a
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/helper.c
    M target/arm/helper.h

  Log Message:
  -----------
  arm/helper.c: re-factor rsqrte and add rsqrte_f16

Much like recpe the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final packing of the result.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c625ff95070e3ef96bd007de744e1d97c881efeb
      
https://github.com/qemu/qemu/commit/c625ff95070e3ef96bd007de744e1d97c881efeb
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 70b4e6a445715519ae55179dc54f6e961ab30c27
      
https://github.com/qemu/qemu/commit/70b4e6a445715519ae55179dc54f6e961ab30c27
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add FP16 FMOV to simd_mod_imm

Only one half-precision instruction has been added to this group.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5c36d89567cfd049a7c59ff219639f788225068f
      
https://github.com/qemu/qemu/commit/5c36d89567cfd049a7c59ff219639f788225068f
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add all FP16 ops in simd_scalar_pairwise

I only needed to do a little light re-factoring to support the
half-precision helpers.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7c93b7741b29b3ffda81a6e9525771b4409db99f
      
https://github.com/qemu/qemu/commit/7c93b7741b29b3ffda81a6e9525771b4409db99f
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: implement simd_scalar_three_reg_same_fp16

This covers the encoding group:

  Advanced SIMD scalar three same FP16

As all the helpers are already there it is simply a case of calling the
existing helpers in the scalar context.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c2c08713a6a5846bbe601d4d1b4f9708ba77efdc
      
https://github.com/qemu/qemu/commit/c2c08713a6a5846bbe601d4d1b4f9708ba77efdc
  Author: Alex Bennée <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: add all single op FP16 to handle_fp_1src_half

This includes FMOV, FABS, FNEG, FSQRT and  FRINT[NPMZAXI]. We re-use
existing helpers to achieve this.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 969b389ee8ba84bc3f2e7ccfa993679fac410ad2
      
https://github.com/qemu/qemu/commit/969b389ee8ba84bc3f2e7ccfa993679fac410ad2
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU

Now we have implemented FP16 we can enable it for the "any" CPU.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
[PMM: split out from an earlier patch in the series]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 201b19d5ce883c6d3b5f6dec2a35a332c4bbec0d
      
https://github.com/qemu/qemu/commit/201b19d5ce883c6d3b5f6dec2a35a332c4bbec0d
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user: Report AArch64 FP16 support via hwcap bits

Set the appropriate Linux hwcap bits to tell the guest binary if we
have implemented half-precision floating point support.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: c22e580c2ad1cccef582e1490e732f254d4ac064
      
https://github.com/qemu/qemu/commit/c22e580c2ad1cccef582e1490e732f254d4ac064
  Author: Alistair Francis <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Update my email address

I am leaving Xilinx, so to avoid having an email address that bounces
update my maintainer address to point to my personal email address.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9db0855e8501365334e859370800c240d25322a2
      
https://github.com/qemu/qemu/commit/9db0855e8501365334e859370800c240d25322a2
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-01 (Thu, 01 Mar 2018)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/arm/vexpress.c
    M hw/core/register.c
    M hw/display/Makefile.objs
    A hw/display/sii9022.c
    M hw/display/trace-events
    M hw/i2c/core.c
    M hw/i2c/i2c-ddc.c
    M hw/ssi/xilinx_spips.c
    M include/exec/helper-head.h
    M include/fpu/softfloat.h
    M include/hw/i2c/i2c.h
    M include/hw/register.h
    M linux-user/elfload.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180301' 
into staging

target-arm queue:
 * update MAINTAINERS for Alistair's new email address
 * add Arm v8.2 FP16 arithmetic extension for linux-user
 * implement display connector emulation for vexpress board
 * xilinx_spips: Enable only two slaves when reading/writing with stripe
 * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
 * hw: register: Run post_write hook on reset

# gpg: Signature made Thu 01 Mar 2018 11:22:46 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180301: (42 commits)
  MAINTAINERS: Update my email address
  linux-user: Report AArch64 FP16 support via hwcap bits
  target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
  arm/translate-a64: add all single op FP16 to handle_fp_1src_half
  arm/translate-a64: implement simd_scalar_three_reg_same_fp16
  arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
  arm/translate-a64: add FP16 FMOV to simd_mod_imm
  arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
  arm/helper.c: re-factor rsqrte and add rsqrte_f16
  arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 FRECPE
  arm/helper.c: re-factor recpe and add recepe_f16
  arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
  arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
  arm/translate-a64: initial decode for simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 x2 ops for simd_indexed
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/8cb340c613ee...9db0855e8501