[Qemu-commits] [qemu/qemu] f9a697: target/arm: Add a core count property

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[Qemu-commits] [qemu/qemu] f9a697: target/arm: Add a core count property

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] f9a697: target/arm: Add a core count property
Date:	Mon, 12 Mar 2018 05:34:30 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: f9a697112ee64180354f98309a5d6b691cc8699d
      
https://github.com/qemu/qemu/commit/f9a697112ee64180354f98309a5d6b691cc8699d
  Author: Alistair Francis <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Add a core count property

The cortex A53 TRM specifies that bits 24 and 25 of the L2CTLR register
specify the number of cores in the processor, not the total number of
cores in the system. To report this correctly on machines with multiple
CPU clusters (ARM's big.LITTLE or Xilinx's ZynqMP) we need to allow
the machine to overwrite this value. To do this let's add an optional
property.

Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8f2ba1f278b3161119646a3b3d510455a8c16fbb
      
https://github.com/qemu/qemu/commit/8f2ba1f278b3161119646a3b3d510455a8c16fbb
  Author: Alistair Francis <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  hw/arm: Set the core count for Xilinx's ZynqMP

Set the ARM CPU core count property for the A53's attached to the Xilnx
ZynqMP machine.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d64e5eabc4c7e20cc8d242545c02198b82e223ca
      
https://github.com/qemu/qemu/commit/d64e5eabc4c7e20cc8d242545c02198b82e223ca
  Author: Andrey Smirnov <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/pci-host/Makefile.objs
    A hw/pci-host/designware.c
    A include/hw/pci-host/designware.h
    M include/hw/pci/pci_ids.h

  Log Message:
  -----------
  pci: Add support for Designware IP block

Add code needed to get a functional PCI subsytem when using in
conjunction with upstream Linux guest (4.13+). Tested to work against
"e1000e" (network adapter, using MSI interrupts) as well as
"usb-ehci" (USB controller, using legacy PCI interrupts).

Based on "i.MX6 Applications Processor Reference Manual" (Document
Number: IMX6DQRM Rev. 4) as well as corresponding dirver in Linux
kernel (circa 4.13 - 4.16 found in drivers/pci/dwc/*)

Signed-off-by: Andrey Smirnov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 757282ada8c64e233825d7e2ef1d8841fdf590fc
      
https://github.com/qemu/qemu/commit/757282ada8c64e233825d7e2ef1d8841fdf590fc
  Author: Andrey Smirnov <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/fsl-imx7.c
    A include/hw/arm/fsl-imx7.h

  Log Message:
  -----------
  i.MX: Add i.MX7 SOC implementation.

The following interfaces are partially or fully emulated:

    * up to 2 Cortex A9 cores (SMP works with PSCI)
    * A7 MPCORE (identical to A15 MPCORE)
    * 4 GPTs modules
    * 7 GPIO controllers
    * 2 IOMUXC controllers
    * 1 CCM module
    * 1 SVNS module
    * 1 SRC module
    * 1 GPCv2 controller
    * 4 eCSPI controllers
    * 4 I2C controllers
    * 7 i.MX UART controllers
    * 2 FlexCAN controllers
    * 2 Ethernet controllers (FEC)
    * 3 SD controllers (USDHC)
    * 4 WDT modules
    * 1 SDMA module
    * 1 GPR module
    * 2 USBMISC modules
    * 2 ADC modules
    * 1 PCIe controller

Tested to boot and work with upstream Linux (4.13+) guest.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Andrey Smirnov <address@hidden>
[PMM: folded a couple of long lines]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 843361ed04017da5f15c3b7a98b2e8849e39a984
      
https://github.com/qemu/qemu/commit/843361ed04017da5f15c3b7a98b2e8849e39a984
  Author: Andrey Smirnov <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/mcimx7d-sabre.c

  Log Message:
  -----------
  Implement support for i.MX7 Sabre board

Implement code needed to set up emulation of MCIMX7SABRE board from
NXP. For more info about the HW see:

https://www.nxp.com/support/developer-resources/hardware-development-tools/sabre-development-system/sabre-board-for-smart-devices-based-on-the-i.mx-7dual-applications-processors:MCIMX7SABRE

Cc: Peter Maydell <address@hidden>
Cc: Jason Wang <address@hidden>
Cc: Philippe Mathieu-Daudé <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Michael S. Tsirkin <address@hidden>
Cc: address@hidden
Cc: address@hidden
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Andrey Smirnov <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 85fc716732bc6e85a634335847999f411269f282
      
https://github.com/qemu/qemu/commit/85fc716732bc6e85a634335847999f411269f282
  Author: Richard Henderson <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M linux-user/aarch64/target_syscall.h
    M linux-user/syscall.c
    M target/arm/cpu.h
    M target/arm/cpu64.c

  Log Message:
  -----------
  linux-user: Implement aarch64 PR_SVE_SET/GET_VL

As an implementation choice, widening VL has zeroed the
previously inaccessible portion of the sve registers.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Acked-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3b505bbae14297d16255f21b9eb02c774a8aa8f6
      
https://github.com/qemu/qemu/commit/3b505bbae14297d16255f21b9eb02c774a8aa8f6
  Author: Richard Henderson <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  aarch64-linux-user: Split out helpers for guest signal handling

Split out helpers from target_setup_frame and target_restore_sigframe
for dealing with general registers, fpsimd registers, and the end record.

When we add support for sve registers, the relative positions of
these will change.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e1eecd1d9d4c1ade32e0499272f04d67a8ae913d
      
https://github.com/qemu/qemu/commit/e1eecd1d9d4c1ade32e0499272f04d67a8ae913d
  Author: Richard Henderson <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  aarch64-linux-user: Remove struct target_aux_context

This changes the qemu signal frame layout to be more like the kernel's,
in that the various records are dynamically allocated rather than fixed
in place by a structure.

For now, all of the allocation is out of uc.tuc_mcontext.__reserved,
so the allocation is actually trivial.  That will change with SVE support.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7a53fb907f64a48bde982f98e38af67b352208e9
      
https://github.com/qemu/qemu/commit/7a53fb907f64a48bde982f98e38af67b352208e9
  Author: Richard Henderson <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  aarch64-linux-user: Add support for EXTRA signal frame records

The EXTRA record allows for additional space to be allocated
beyon what is currently reserved.  Add code to emit and read
this record type.

Nothing uses extra space yet.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8c5931de0ac77388096d79cebf6341471cf2313e
      
https://github.com/qemu/qemu/commit/8c5931de0ac77388096d79cebf6341471cf2313e
  Author: Richard Henderson <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  aarch64-linux-user: Add support for SVE signal frame records

Depending on the currently selected size of the SVE vector registers,
we can either store the data within the "standard" allocation, or we
may beedn to allocate additional space with an EXTRA record.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0bbabbb414387d8710ca9fe43c8d02bc898c4048
      
https://github.com/qemu/qemu/commit/0bbabbb414387d8710ca9fe43c8d02bc898c4048
  Author: Thomas Huth <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs

  Log Message:
  -----------
  hw/arm: Use more CONFIG switches for the object files

A lot of ARM object files are linked into the executable unconditionally,
even though we have corresponding CONFIG switches like CONFIG_PXA2XX or
CONFIG_OMAP. We should make sure to use these switches in the Makefile so
that the users can disable certain unwanted boards and devices more easily.
While we're at it, also add some new switches for the boards that do not
have a CONFIG option yet.

Signed-off-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 36f876cea4947417c14c2f0798f1db374a4e8bea
      
https://github.com/qemu/qemu/commit/36f876cea4947417c14c2f0798f1db374a4e8bea
  Author: Marc-André Lureau <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  arm: fix load ELF error leak

Spotted by ASAN:
QTEST_QEMU_BINARY=aarch64-softmmu/qemu-system-aarch64 tests/boot-serial-test

Direct leak of 48 byte(s) in 1 object(s) allocated from:
    #0 0x7ff8a9b0ca38 in __interceptor_calloc (/lib64/libasan.so.4+0xdea38)
    #1 0x7ff8a8ea7f75 in g_malloc0 ../glib/gmem.c:124
    #2 0x55fef3d99129 in error_setv /home/elmarco/src/qemu/util/error.c:59
    #3 0x55fef3d99738 in error_setg_internal 
/home/elmarco/src/qemu/util/error.c:95
    #4 0x55fef323acb2 in load_elf_hdr 
/home/elmarco/src/qemu/hw/core/loader.c:393
    #5 0x55fef2d15776 in arm_load_elf /home/elmarco/src/qemu/hw/arm/boot.c:830
    #6 0x55fef2d16d39 in arm_load_kernel_notify 
/home/elmarco/src/qemu/hw/arm/boot.c:1022
    #7 0x55fef3dc634d in notifier_list_notify 
/home/elmarco/src/qemu/util/notify.c:40
    #8 0x55fef2fc3182 in qemu_run_machine_init_done_notifiers 
/home/elmarco/src/qemu/vl.c:2716
    #9 0x55fef2fcbbd1 in main /home/elmarco/src/qemu/vl.c:4679
    #10 0x7ff89dfed009 in __libc_start_main (/lib64/libc.so.6+0x21009)

Signed-off-by: Marc-André Lureau <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2764040785b3400e3aafab74b8448ad24e8ae14d
      
https://github.com/qemu/qemu/commit/2764040785b3400e3aafab74b8448ad24e8ae14d
  Author: Marc-André Lureau <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  arm: avoid heap-buffer-overflow in load_aarch64_image

Spotted by ASAN:

address@hidden:~/src/qemu/build (master *%)$ 
QTEST_QEMU_BINARY=aarch64-softmmu/qemu-system-aarch64 tests/boot-serial-test
/aarch64/boot-serial/virt: ** (process:19740): DEBUG: 18:39:30.275: foo 
/tmp/qtest-boot-serial-cXaS94D
=================================================================
==19740==ERROR: AddressSanitizer: heap-buffer-overflow on address 
0x603000069648 at pc 0x7f1d2201cc54 bp 0x7fff331f6a40 sp 0x7fff331f61e8
READ of size 4 at 0x603000069648 thread T0
    #0 0x7f1d2201cc53  (/lib64/libasan.so.4+0xafc53)
    #1 0x55bc86685ee3 in load_aarch64_image 
/home/elmarco/src/qemu/hw/arm/boot.c:894
    #2 0x55bc86687217 in arm_load_kernel_notify 
/home/elmarco/src/qemu/hw/arm/boot.c:1047
    #3 0x55bc877363b5 in notifier_list_notify 
/home/elmarco/src/qemu/util/notify.c:40
    #4 0x55bc869331ea in qemu_run_machine_init_done_notifiers 
/home/elmarco/src/qemu/vl.c:2716
    #5 0x55bc8693bc39 in main /home/elmarco/src/qemu/vl.c:4679
    #6 0x7f1d1652c009 in __libc_start_main (/lib64/libc.so.6+0x21009)
    #7 0x55bc86255cc9 in _start 
(/home/elmarco/src/qemu/build/aarch64-softmmu/qemu-system-aarch64+0x1ae5cc9)

Signed-off-by: Marc-André Lureau <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c4487d76d52dcc050c1e144ab90c0565a5fc716e
      
https://github.com/qemu/qemu/commit/c4487d76d52dcc050c1e144ab90c0565a5fc716e
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/kvm.c
    M target/arm/kvm32.c
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  target/arm: Query host CPU features on-demand at instance init

Currently we query the host CPU features in the class init function
for the TYPE_ARM_HOST_CPU class, so that we can later copy them
from the class object into the instance object in the object
instance init function. This is awkward for implementing "-cpu max",
which should work like "-cpu host" for KVM but like "cpu with all
implemented features" for TCG.

Move the place where we store the information about the host CPU from
a class object to static variables in kvm.c, and then in the instance
init function call a new kvm_arm_set_cpu_features_from_host()
function which will query the host kernel if necessary and then
fill in the CPU instance fields.

This allows us to drop the special class struct and class init
function for TYPE_ARM_HOST_CPU entirely.

We can't delay the probe until realize, because the ARM
instance_post_init hook needs to look at the feature bits we
set, so we need to do it in the initfn. This is safe because
the probing doesn't affect the actual VM state (it creates a
separate scratch VM to do its testing), but the probe might fail.
Because we can't report errors in retrieving the host features
in the initfn, we check this belatedly in the realize function
(the intervening code will be able to cope with the relevant
fields in the CPU structure being zero).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 86f0a186d6f05c429e982628fe5a2aa7ea1e2724
      
https://github.com/qemu/qemu/commit/86f0a186d6f05c429e982628fe5a2aa7ea1e2724
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/kvm.c

  Log Message:
  -----------
  target/arm: Move definition of 'host' cpu type into cpu.c

Move the definition of the 'host' cpu type into cpu.c, where all the
other CPU types are defined.  We can do this now we've decoupled it
from the KVM-specific host feature probing.  This means we now create
the type unconditionally (assuming we were built with KVM support at
all), but if you try to use it without -enable-kvm this will end
up in the "host cpu probe failed and KVM not enabled" path in
arm_cpu_realizefn(), for an appropriate error message.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: bab52d4bba3f22921a690a887b4bd0342f2754cd
      
https://github.com/qemu/qemu/commit/bab52d4bba3f22921a690a887b4bd0342f2754cd
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M target/arm/cpu-qom.h
    M target/arm/cpu.c
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Add "-cpu max" support

Add support for "-cpu max" for ARM guests. This CPU type behaves
like "-cpu host" when KVM is enabled, and like a system CPU with
the maximum possible feature set otherwise. (Note that this means
it won't be migratable across versions, as we will likely add
features to it in future.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: a0032cc5427d0d396aa0a9383ad9980533448ea4
      
https://github.com/qemu/qemu/commit/a0032cc5427d0d396aa0a9383ad9980533448ea4
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Make 'any' CPU just an alias for 'max'

Now we have a working '-cpu max', the linux-user-only
'any' CPU is pretty much the same thing, so implement it
that way.

For the moment we don't add any of the extra feature bits
to the system-emulation "max", because we don't set the
ID register bits we would need to to advertise those
features as present.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 9076ddb3f60a0583b68de6b20ec2b664f08f71cc
      
https://github.com/qemu/qemu/commit/9076ddb3f60a0583b68de6b20ec2b664f08f71cc
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Add "max" to the list of CPU types "virt" supports

Allow the virt board to support '-cpu max' in the same way
it already handles '-cpu host'.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: dc16538a985b1ed9175dc69382b0467e15e50949
      
https://github.com/qemu/qemu/commit/dc16538a985b1ed9175dc69382b0467e15e50949
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Support -machine gic-version=max

Add support for passing 'max' to -machine gic-version. By analogy
with the -cpu max option, this picks the "best available" GIC version
whether you're using KVM or TCG, so it behaves like 'host' when
using KVM, and gives you GICv3 when using TCG.

Also like '-cpu host', using -machine gic-version=max' means there
is no guarantee of migration compatibility between QEMU versions;
in future 'max' might mean '4'.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 586634b9a8a6b5c0ce7180d332814393fe7dbfa8
      
https://github.com/qemu/qemu/commit/586634b9a8a6b5c0ce7180d332814393fe7dbfa8
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/sd/sd.c

  Log Message:
  -----------
  sdcard: Do not trace CMD55, except when we already expect an ACMD

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2ed61fb57b960b1f94501de634da1b8c26ff520f
      
https://github.com/qemu/qemu/commit/2ed61fb57b960b1f94501de634da1b8c26ff520f
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/sd/Makefile.objs
    M hw/sd/sd.c
    A hw/sd/sdmmc-internal.c
    M hw/sd/sdmmc-internal.h
    M hw/sd/trace-events

  Log Message:
  -----------
  sdcard: Display command name when tracing CMD/ACMD

The SDBus will reuse these functions, so we put them in a new source file.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: slight wordsmithing of comments, added note that string
 returned does not need to be freed]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 75a96f5e1cf8a70c805500ea5a3108ebbc2bd1f7
      
https://github.com/qemu/qemu/commit/75a96f5e1cf8a70c805500ea5a3108ebbc2bd1f7
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/sd/sd.c
    M hw/sd/trace-events

  Log Message:
  -----------
  sdcard: Display which protocol is used when tracing (SD or SPI)

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c3fb03f7ec4a6a744845722817621fc47ac97d6
      
https://github.com/qemu/qemu/commit/0c3fb03f7ec4a6a744845722817621fc47ac97d6
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/sd/sd.c

  Log Message:
  -----------
  sdcard: Add the Tuning Command (CMD19)

>From the "Physical Layer Simplified Specification Version 3.01":

  A known data block ("Tuning block") can be used to tune sampling
  point for tuning required hosts. [...]
  This procedure gives the system optimal timing for each specific
  host and card combination and compensates for static delays in
  the timing budget including process, voltage and different PCB
  loads and skews. [...]
  Data block, carried by DAT[3:0], contains a pattern for tuning
  sampling position to receive data on the CMD and DAT[3:0] line.

[based on a patch from Alistair Francis <address@hidden>
 from qemu/xilinx tag xilinx-v2015.2]
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 08022a916cee12d1c41540893b7e4ade36ef144b
      
https://github.com/qemu/qemu/commit/08022a916cee12d1c41540893b7e4ade36ef144b
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M hw/sd/sdhci.c

  Log Message:
  -----------
  sdhci: Fix a typo in comment

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 076a0fc32a73a9b960e0f73f04a531bc1bd94308
      
https://github.com/qemu/qemu/commit/076a0fc32a73a9b960e0f73f04a531bc1bd94308
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add entries for SD (SDHCI, SDBus, SDCard)

After spending months studying all the different SD Specifications
from the SD Association, voluntarily add myself as maintainer
for the SD code.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5df089564be6e6a6b1bc79207f74b5b7ed4e1277
      
https://github.com/qemu/qemu/commit/5df089564be6e6a6b1bc79207f74b5b7ed4e1277
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-12 (Mon, 12 Mar 2018)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    M hw/arm/boot.c
    A hw/arm/fsl-imx7.c
    A hw/arm/mcimx7d-sabre.c
    M hw/arm/virt.c
    M hw/arm/xlnx-zynqmp.c
    M hw/pci-host/Makefile.objs
    A hw/pci-host/designware.c
    M hw/sd/Makefile.objs
    M hw/sd/sd.c
    M hw/sd/sdhci.c
    A hw/sd/sdmmc-internal.c
    M hw/sd/sdmmc-internal.h
    M hw/sd/trace-events
    A include/hw/arm/fsl-imx7.h
    A include/hw/pci-host/designware.h
    M include/hw/pci/pci_ids.h
    M linux-user/aarch64/target_syscall.h
    M linux-user/signal.c
    M linux-user/syscall.c
    M target/arm/cpu-qom.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/kvm.c
    M target/arm/kvm32.c
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180309' 
into staging

target-arm queue:
 * i.MX: Add i.MX7 SOC implementation and i.MX7 Sabre board
 * Report the correct core count in A53 L2CTLR on the ZynqMP board
 * linux-user: preliminary SVE support work (signal handling)
 * hw/arm/boot: fix memory leak in case of error loading ELF file
 * hw/arm/boot: avoid reading off end of buffer if passed very
   small image file
 * hw/arm: Use more CONFIG switches for the object files
 * target/arm: Add "-cpu max" support
 * hw/arm/virt: Support -machine gic-version=max
 * hw/sd: improve debug tracing
 * hw/sd: sdcard: Add the Tuning Command (CMD 19)
 * MAINTAINERS: add Philippe as odd-fixes maintainer for SD

# gpg: Signature made Fri 09 Mar 2018 17:24:23 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180309: (25 commits)
  MAINTAINERS: Add entries for SD (SDHCI, SDBus, SDCard)
  sdhci: Fix a typo in comment
  sdcard: Add the Tuning Command (CMD19)
  sdcard: Display which protocol is used when tracing (SD or SPI)
  sdcard: Display command name when tracing CMD/ACMD
  sdcard: Do not trace CMD55, except when we already expect an ACMD
  hw/arm/virt: Support -machine gic-version=max
  hw/arm/virt: Add "max" to the list of CPU types "virt" supports
  target/arm: Make 'any' CPU just an alias for 'max'
  target/arm: Add "-cpu max" support
  target/arm: Move definition of 'host' cpu type into cpu.c
  target/arm: Query host CPU features on-demand at instance init
  arm: avoid heap-buffer-overflow in load_aarch64_image
  arm: fix load ELF error leak
  hw/arm: Use more CONFIG switches for the object files
  aarch64-linux-user: Add support for SVE signal frame records
  aarch64-linux-user: Add support for EXTRA signal frame records
  aarch64-linux-user: Remove struct target_aux_context
  aarch64-linux-user: Split out helpers for guest signal handling
  linux-user: Implement aarch64 PR_SVE_SET/GET_VL
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/12c06d6f967a...5df089564be6
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