[Qemu-commits] [qemu/qemu] c2d964: target/arm: Fix crash on conditional instruction i...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c2d9644e6d517170bf6520f633628259a8460d48
      
https://github.com/qemu/qemu/commit/c2d9644e6d517170bf6520f633628259a8460d48
  Author: Roman Kapl <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Fix crash on conditional instruction in an IT block

If an instruction is conditional (like CBZ) and it is executed
conditionally (using the ITx instruction), a jump to an undefined
label is generated, and QEMU crashes.

CBZ in IT block is an UNPREDICTABLE behavior, but we should not
crash.  Honouring the condition code is allowed by the spec in this
case (constrained unpredictable, ARMv8, section K1.1.7), and matches
what we do for other "UNPREDICTABLE inside an IT block" instructions.

Fix the 'skip on condition' code to create a new label only if it
does not already exist.  Previously multiple labels were created, but
only the last one of them was set.

Signed-off-by: Roman Kapl <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: fixed ^ 1 being applied to wrong argument, fixed typo]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 67c791f611c6d9513a2ae4129ce861f4c655ae0f
      
https://github.com/qemu/qemu/commit/67c791f611c6d9513a2ae4129ce861f4c655ae0f
  Author: Stefan Hajnoczi <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M docs/generic-loader.txt

  Log Message:
  -----------
  docs/generic-loader: mention U-Boot and Intel HEX executable formats

The generic loader device supports the U-Boot and Intel HEX executable
formats in addition to the document raw and ELF formats.  Reword the
documentation to include these formats and explain how various options
depend on the executable format.

Signed-off-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 84be3ef1defeefc4ef157f8657d178d204ec0f3a
      
https://github.com/qemu/qemu/commit/84be3ef1defeefc4ef157f8657d178d204ec0f3a
  Author: Jia He <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/intc/arm_gicv3_its_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: downgrade error_report to warn_report in 
kvm_arm_its_reset

In scripts/arch-run.bash of kvm-unit-tests, it will check the qemu
output log with:
if [ -z "$(echo "$errors" | grep -vi warning)" ]; then

Thus without the warning prefix, all of the test fail.

Since it is not unrecoverable error in kvm_arm_its_reset for
current implementation, downgrading the report from error to
warn makes sense.

Signed-off-by: Jia He <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3c54cf7705f243c0d37f254abd0131ab69ae94e5
      
https://github.com/qemu/qemu/commit/3c54cf7705f243c0d37f254abd0131ab69ae94e5
  Author: Hans-Erik Floryd <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/char/imx_serial.c
    M include/hw/char/imx_serial.h

  Log Message:
  -----------
  imx_serial: Generate interrupt on receive data ready if enabled

Generate an interrupt if USR2_RDR and UCR4_DREN are both set.

Signed-off-by: Hans-Erik Floryd <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 55b53c718b2f684793eeefcf1c1a548ee97e23aa
      
https://github.com/qemu/qemu/commit/55b53c718b2f684793eeefcf1c1a548ee97e23aa
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Correct typo in HAMAIR1 regdef name

We implement the HAMAIR1 register as RAZ/WI; we had a typo in the
regdef, though, and were incorrectly naming it HMAIR1 (which is
a different register which we also implement as RAZ/WI).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden


  Commit: b5ede85bfb7ba1a8f6086494c82f400b29969f65
      
https://github.com/qemu/qemu/commit/b5ede85bfb7ba1a8f6086494c82f400b29969f65
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs

ARMCPRegInfo structs will default to .cp = 15 if they
are ARM_CP_STATE_BOTH, but not if they are ARM_CP_STATE_AA32
(because a coprocessor number of 0 is valid for AArch32).
We forgot to explicitly set .cp = 15 for the HMAIR1 and
HAMAIR1 regdefs, which meant they would UNDEF when the guest
tried to access them under cp15.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden


  Commit: d79e0c0608899428281a17c414ccf1a82d86ab85
      
https://github.com/qemu/qemu/commit/d79e0c0608899428281a17c414ccf1a82d86ab85
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement AArch32 HVBAR

Implement the AArch32 HVBAR register; we can do this just by
making the existing VBAR_EL2 regdefs be STATE_BOTH.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden


  Commit: cba517c31e7df8932c4473c477a0f01d8a0adc48
      
https://github.com/qemu/qemu/commit/cba517c31e7df8932c4473c477a0f01d8a0adc48
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement AArch32 Hyp FARs

The AArch32 virtualization extensions support these fault address
registers:
 * HDFAR: aliased with AArch64 FAR_EL2[31:0] and AArch32 DFAR(S)
 * HIFAR: aliased with AArch64 FAR_EL2[63:32] and AArch32 IFAR(S)

Implement the accessors for these. This fixes in passing a bug
where we weren't implementing the "RES0 from EL3 if EL2 not
implemented" behaviour for AArch64 FAR_EL2.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden


  Commit: 68e78e332cb1c3f8b0317a0443acb2b5e190f0dd
      
https://github.com/qemu/qemu/commit/68e78e332cb1c3f8b0317a0443acb2b5e190f0dd
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2

The AArch32 HSR is the equivalent of AArch64 ESR_EL2;
we can implement it by marking our existing ESR_EL2 regdef
as STATE_BOTH. It also needs to be "RES0 from EL3 if
EL2 not implemented", so add the missing stanza to
el3_no_el2_cp_reginfo.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden


  Commit: aec4dd09f172ee64c19222b78269d5952fd9c1dc
      
https://github.com/qemu/qemu/commit/aec4dd09f172ee64c19222b78269d5952fd9c1dc
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M target/arm/op_helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)

The MSR (banked) and MRS (banked) instructions allow accesses to ELR_Hyp
from either Monitor or Hyp mode. Our translate time check
was overly strict and only permitted access from Monitor mode.

The runtime check we do in msr_mrs_banked_exc_checks() had the
correct code in it, but never got there because of the earlier
"currmode == tgtmode" check. Special case ELR_Hyp.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden


  Commit: 55c544ed2709bd202e71e77ddfe3ea0327852211
      
https://github.com/qemu/qemu/commit/55c544ed2709bd202e71e77ddfe3ea0327852211
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Implement AArch32 ERET instruction

ARMv7VE introduced the ERET instruction, which is necessary to
return from an exception taken to Hyp mode. Implement this.
In A32 encoding it is a completely new encoding; in T32 it
is an adjustment of the behaviour of the existing
"SUBS PC, LR, #<imm8>" instruction.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden


  Commit: 22907d2b81c4702c0d226ad1364605dc9adac232
      
https://github.com/qemu/qemu/commit/22907d2b81c4702c0d226ad1364605dc9adac232
  Author: Andrew Jones <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Add virt-3.1 machine type

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6bfd06da6e3b293c9d7f561ea6afc857267c9ecd
      
https://github.com/qemu/qemu/commit/6bfd06da6e3b293c9d7f561ea6afc857267c9ecd
  Author: Hans-Erik Floryd <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/sd/sdhci-internal.h
    M hw/sd/sdhci.c

  Log Message:
  -----------
  sdhci: add i.MX SD Stable Clock bit

Add the ESDHC PRSSTAT_SDSTB bit, using the value of SDHC_CLOCK_INT_STABLE.
Freescale recommends checking this bit when changing clock frequency.

Signed-off-by: Hans-Erik Floryd <address@hidden>
Message-id: address@hidden
[PMM: fixed indentation]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5321fa68fdb7e285d60d8050057129027a8c1c63
      
https://github.com/qemu/qemu/commit/5321fa68fdb7e285d60d8050057129027a8c1c63
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr code

We now support direct execution from MMIO regions in the
core memory subsystem. This means that we don't need to
have device-specific support for it, and we can remove
the request_ptr handling from the Xilinx SPIPS device.
(It was broken anyway due to race conditions, and disabled
by default.)

This device is the only in-tree user of this API.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Message-id: address@hidden


  Commit: 8c1c245378f646c18ee03a24154bd611e6abe52e
      
https://github.com/qemu/qemu/commit/8c1c245378f646c18ee03a24154bd611e6abe52e
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M include/exec/memory.h
    M memory.c

  Log Message:
  -----------
  memory: Remove MMIO request_ptr APIs

Remove the obsolete MMIO request_ptr APIs; they have no
users now.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Message-id: address@hidden


  Commit: 3eff40dbf44896a8180c86c84dbdefb2eb173fbe
      
https://github.com/qemu/qemu/commit/3eff40dbf44896a8180c86c84dbdefb2eb173fbe
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/misc/Makefile.objs
    R hw/misc/mmio_interface.c
    R include/hw/misc/mmio_interface.h

  Log Message:
  -----------
  hw/misc: Remove mmio_interface device

The mmio_interface device was a purely internal artifact
of the implementation of the memory subsystem's request_ptr
APIs. Now that we have removed those APIs, we can remove
the mmio_interface device too.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Message-id: address@hidden


  Commit: 62b9cf0a77b4dd5571a948d798d4604f4ae6bcd5
      
https://github.com/qemu/qemu/commit/62b9cf0a77b4dd5571a948d798d4604f4ae6bcd5
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/timer/m48t59.c

  Log Message:
  -----------
  hw/timer/m48t59: Move away from old_mmio accessors

Move the m48t59 device away from using old_mmio MemoryRegionOps
accessors.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Mark Cave-Ayland <address@hidden>
Message-id: address@hidden


  Commit: 050c2ea07b18b77c7562512a2b73e86e48c5c4b7
      
https://github.com/qemu/qemu/commit/050c2ea07b18b77c7562512a2b73e86e48c5c4b7
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M MAINTAINERS
    M Makefile.objs
    M default-configs/arm-softmmu.mak
    M hw/watchdog/Makefile.objs
    A hw/watchdog/cmsdk-apb-watchdog.c
    A hw/watchdog/trace-events
    A include/hw/watchdog/cmsdk-apb-watchdog.h

  Log Message:
  -----------
  hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module

The Arm Cortex-M System Design Kit includes a simple watchdog module
based on a 32-bit down-counter. Implement this.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 514b4f361b65c49303877829561faad5e1d2463c
      
https://github.com/qemu/qemu/commit/514b4f361b65c49303877829561faad5e1d2463c
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/arm/armv7m.c
    M hw/intc/armv7m_nvic.c
    M hw/intc/trace-events

  Log Message:
  -----------
  nvic: Expose NMI line

On real v7M hardware, the NMI line is an externally visible signal
that an SoC or board can toggle to assert an NMI. Expose it in
our QEMU NVIC and armv7m container objects so that a board model
can wire it up if it needs to.

In particular, the MPS2 watchdog is wired to NMI.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: aa74e355f12438888eacdd8f3c2fc910b1b621a7
      
https://github.com/qemu/qemu/commit/aa74e355f12438888eacdd8f3c2fc910b1b621a7
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M MAINTAINERS
    M hw/dma/pl080.c
    A include/hw/dma/pl080.h

  Log Message:
  -----------
  hw/dma/pl080: Allow use as embedded-struct device

Create a new include file for the pl081's device struct,
type macros, etc, so that it can be instantiated using
the "embedded struct" coding style.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 6d0ed6ba6c1aa0201326d4f0072e91983495bb52
      
https://github.com/qemu/qemu/commit/6d0ed6ba6c1aa0201326d4f0072e91983495bb52
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/dma/pl080.c
    M include/hw/dma/pl080.h

  Log Message:
  -----------
  hw/dma/pl080: Support all three interrupt lines

The PL080 and PL081 have three outgoing interrupt lines:
 * DMACINTERR signals DMA errors
 * DMACINTTC is the DMA count interrupt
 * DMACINTR is a combined interrupt, the logical OR of the other two

We currently only implement DMACINTR, because that's all the
realview and versatile boards needed, but the instances of the
PL081 in the MPS2 firmware images use all three interrupt lines.
Implement the missing DMACINTERR and DMACINTTC.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 112a829f8f0add64f73bfea66c153355ea596da9
      
https://github.com/qemu/qemu/commit/112a829f8f0add64f73bfea66c153355ea596da9
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/arm/realview.c
    M hw/arm/versatilepb.c
    M hw/dma/pl080.c
    M include/hw/dma/pl080.h

  Log Message:
  -----------
  hw/dma/pl080: Don't use CPU address space for DMA accesses

Currently our PL080/PL081 model uses a combination of the CPU's
address space (via cpu_physical_memory_{read,write}()) and the
system address space for performing DMA accesses.

For the PL081s in the MPS FPGA images, their DMA accesses
must go via Master Security Controllers. Switch the
PL080/PL081 model to take a MemoryRegion property which
defines its downstream for making DMA accesses.

Since the PL08x are only used in two board models, we
make provision of the 'downstream' link mandatory and convert
both users at once, rather than having it be optional with
a default to the system address space.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: c193304d4f9ef21c51ff412f6279ad459eedd438
      
https://github.com/qemu/qemu/commit/c193304d4f9ef21c51ff412f6279ad459eedd438
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/dma/pl080.c

  Log Message:
  -----------
  hw/dma/pl080: Provide device reset function

The PL080/PL081 model is missing a reset function; implement it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 156448ab640baaeca185787eb303fe4d63edca26
      
https://github.com/qemu/qemu/commit/156448ab640baaeca185787eb303fe4d63edca26
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/dma/pl080.c

  Log Message:
  -----------
  hw/dma/pl080: Correct bug in register address decode logic

A bug in the handling of the register address decode logic
for the PL08x meant that we were incorrectly treating
accesses to the DMA channel registers (DMACCxSrcAddr,
DMACCxDestaddr, DMACCxLLI, DMACCxControl, DMACCxConfiguration)
as bad offsets. Fix this long-standing bug.

Fixes: https://bugs.launchpad.net/qemu/+bug/1637974
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: b85fad1588e812566f897f747e38da345a7016d6
      
https://github.com/qemu/qemu/commit/b85fad1588e812566f897f747e38da345a7016d6
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M hw/dma/pl080.c

  Log Message:
  -----------
  hw/dma/pl080: Remove hw_error() if DMA is enabled

The PL08x model currently will unconditionally call hw_error()
if the DMA engine is enabled by the guest. This has been
present since the PL080 model was edded in 2006, and is
presumably either unintentional debug code left enabled,
or a guard against untested DMA engine code being used.

Remove the hw_error(), since we now have a guest which
will actually try to use the DMA engine (the self-test
binary for the AN505 MPS2 FPGA image).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 62c34848efb41f0e81af0c6b4f1d5d577039eec9
      
https://github.com/qemu/qemu/commit/62c34848efb41f0e81af0c6b4f1d5d577039eec9
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-20 (Mon, 20 Aug 2018)

  Changed paths:
    M MAINTAINERS
    M Makefile.objs
    M default-configs/arm-softmmu.mak
    M docs/generic-loader.txt
    M hw/arm/armv7m.c
    M hw/arm/realview.c
    M hw/arm/versatilepb.c
    M hw/arm/virt.c
    M hw/char/imx_serial.c
    M hw/dma/pl080.c
    M hw/intc/arm_gicv3_its_kvm.c
    M hw/intc/armv7m_nvic.c
    M hw/intc/trace-events
    M hw/misc/Makefile.objs
    R hw/misc/mmio_interface.c
    M hw/sd/sdhci-internal.h
    M hw/sd/sdhci.c
    M hw/ssi/xilinx_spips.c
    M hw/timer/m48t59.c
    M hw/watchdog/Makefile.objs
    A hw/watchdog/cmsdk-apb-watchdog.c
    A hw/watchdog/trace-events
    M include/exec/memory.h
    M include/hw/char/imx_serial.h
    A include/hw/dma/pl080.h
    R include/hw/misc/mmio_interface.h
    A include/hw/watchdog/cmsdk-apb-watchdog.h
    M memory.c
    M target/arm/helper.c
    M target/arm/op_helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180820' 
into staging

target-arm queue:
 * Fix crash on conditional instruction in an IT block
 * docs/generic-loader: mention U-Boot and Intel HEX executable formats
 * hw/intc/arm_gicv3_its: downgrade error_report to warn_report in 
kvm_arm_its_reset
 * imx_serial: Generate interrupt on receive data ready if enabled
 * Fix various minor bugs in AArch32 Hyp related coprocessor registers
 * Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)
 * Implement AArch32 ERET instruction
 * hw/arm/virt: Add virt-3.1 machine type
 * sdhci: add i.MX SD Stable Clock bit
 * Remove now-obsolete MMIO request_ptr APIs
 * hw/timer/m48t59: Move away from old_mmio accessors
 * hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module
 * nvic: Expose NMI line
 * hw/dma/pl080: cleanups and new features required for use in MPS boards

# gpg: Signature made Mon 20 Aug 2018 11:30:12 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180820: (25 commits)
  hw/dma/pl080: Remove hw_error() if DMA is enabled
  hw/dma/pl080: Correct bug in register address decode logic
  hw/dma/pl080: Provide device reset function
  hw/dma/pl080: Don't use CPU address space for DMA accesses
  hw/dma/pl080: Support all three interrupt lines
  hw/dma/pl080: Allow use as embedded-struct device
  nvic: Expose NMI line
  hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module
  hw/timer/m48t59: Move away from old_mmio accessors
  hw/misc: Remove mmio_interface device
  memory: Remove MMIO request_ptr APIs
  hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr code
  sdhci: add i.MX SD Stable Clock bit
  hw/arm/virt: Add virt-3.1 machine type
  target/arm: Implement AArch32 ERET instruction
  target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)
  target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2
  target/arm: Implement AArch32 Hyp FARs
  target/arm: Implement AArch32 HVBAR
  target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/627fce617868...62c34848efb4
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