[Qemu-commits] [qemu/qemu] cdf634: hw/misc/armsse-mhu.c: Model the SSE-200 Message Ha...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: cdf63440eaaee531e2f5b84a833a707f3825e2ac
      
https://github.com/qemu/qemu/commit/cdf63440eaaee531e2f5b84a833a707f3825e2ac
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/misc/Makefile.objs
    A hw/misc/armsse-mhu.c
    M hw/misc/trace-events
    A include/hw/misc/armsse-mhu.h

  Log Message:
  -----------
  hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit

Implement a model of the Message Handling Unit (MHU) found in
the Arm SSE-200. This is a simple device which just contains
some registers which allow the two cores of the SSE-200
to raise interrupts on each other.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 68d6b36f7f737485b7c5725a5d746d6302e1cfa1
      
https://github.com/qemu/qemu/commit/68d6b36f7f737485b7c5725a5d746d6302e1cfa1
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Wire up the MHUs

Create and connect the MHUs in the SSE-200.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: f9f62e4c376c6e737e162209b197dcda690e9f81
      
https://github.com/qemu/qemu/commit/f9f62e4c376c6e737e162209b197dcda690e9f81
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm/cpu: Allow init-svtor property to be set after realize

Make the M-profile "init-svtor" property be settable after realize.
This matches the hardware, where this is a config signal which
is sampled on CPU reset and can thus be changed between one
reset and another. To do this we have to change the API we
use to add the property.

(We will need this capability for the SSE-200.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: ea824b97424a46140bdcfc27d78da6c7f4ec24ff
      
https://github.com/qemu/qemu/commit/ea824b97424a46140bdcfc27d78da6c7f4ec24ff
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M target/arm/arm-powerctl.c
    M target/arm/arm-powerctl.h

  Log Message:
  -----------
  target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()

Currently the Arm arm-powerctl.h APIs allow:
 * arm_set_cpu_on(), which powers on a CPU and sets its
   initial PC and other startup state
 * arm_reset_cpu(), which resets a CPU which is already on
   (and fails if the CPU is powered off)

but there is no way to say "power on a CPU as if it had
just come out of reset and don't do anything else to it".

Add a new function arm_set_cpu_on_and_reset(), which does this.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 394e10d2bb300e4445b0ce37f6d138302f2ff04e
      
https://github.com/qemu/qemu/commit/394e10d2bb300e4445b0ce37f6d138302f2ff04e
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M hw/misc/iotkit-sysctl.c
    M include/hw/misc/iotkit-sysctl.h

  Log Message:
  -----------
  hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name

The iotkit-sysctl device has a register it names INITSVRTOR0.
This is actually a typo present in the IoTKit documentation
and also in part of the SSE-200 documentation:  it should be
INITSVTOR0 because it is specifying the initial value of the
Secure VTOR register in the CPU. Correct the typo.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 0483641418643d5d4cc4d1328fe7acc4ab36c709
      
https://github.com/qemu/qemu/commit/0483641418643d5d4cc4d1328fe7acc4ab36c709
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M hw/misc/iotkit-sysctl.c
    M include/hw/misc/iotkit-sysctl.h

  Log Message:
  -----------
  hw/arm/iotkit-sysctl: Add SSE-200 registers

The SYSCTL block in the SSE-200 has some extra registers that
are not present in the IoTKit version. Add these registers
(as reads-as-written stubs), enabled by a new QOM property.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 0f862986e02f5cc188e56b8bd6a8a203091c1dc2
      
https://github.com/qemu/qemu/commit/0f862986e02f5cc188e56b8bd6a8a203091c1dc2
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M hw/misc/iotkit-sysctl.c

  Log Message:
  -----------
  hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*

The CPUWAIT register acts as a sort of power-control: if a bit
in it is 1 then the CPU will have been forced into waiting
when the system was reset (which in QEMU we model as the
CPU starting powered off). Writing a 0 to the register will
allow the CPU to boot (for QEMU, we model this as powering
it on). Note that writing 0 to the register does not power
off a CPU.

For this to work correctly we need to also honour the
INITSVTOR* registers, which let the guest control where the
CPU will load its SP and PC from when it comes out of reset.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: aab7a3786f085cb4c6842c3c8ea0c86e2c835248
      
https://github.com/qemu/qemu/commit/aab7a3786f085cb4c6842c3c8ea0c86e2c835248
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M hw/misc/iotkit-sysctl.c
    M include/hw/misc/iotkit-sysctl.h

  Log Message:
  -----------
  hw/arm/armsse: Unify init-svtor and cpuwait handling

At the moment the handling of init-svtor and cpuwait initial
values is split between armsse.c and iotkit-sysctl.c:
the code in armsse.c sets the initial state of the CPU
object by setting the init-svtor and start-powered-off
properties, but the iotkit-sysctl.c code has its own
code setting the reset values of its registers (which are
then used when updating the CPU when the guest makes
runtime changes).

Clean this up by making the armsse.c code set properties on the
iotkit-sysctl object to define the initial values of the
registers, so they always match the initial CPU state,
and update the comments in armsse.c accordingly.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 602f6e42cfbfe9278be34e9b91d2ceb695837e02
      
https://github.com/qemu/qemu/commit/602f6e42cfbfe9278be34e9b91d2ceb695837e02
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/kvm32.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions

Instead of gating the A32/T32 FP16 conversion instructions on
the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
looking at ID register bits. In this case MVFR1 fields FPHP
and SIMDHP indicate the presence of these insns.

This change doesn't alter behaviour for any of our CPUs.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: c0c760afe800b60b48c80ddf3509fec413594778
      
https://github.com/qemu/qemu/commit/c0c760afe800b60b48c80ddf3509fec413594778
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Gate "miscellaneous FP" insns by ID register field

There is a set of VFP instructions which we implement in
disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
These were all first introduced in v8 for A-profile, but in
M-profile they appeared in v7M. Gate them on the MVFR2
FPMisc field instead, and rename the function appropriately.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 942f99c825fc94c8b1a402fea128a41339cccee9
      
https://github.com/qemu/qemu/commit/942f99c825fc94c8b1a402fea128a41339cccee9
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/kvm32.c
    M target/arm/kvm64.c
    M target/arm/machine.c

  Log Message:
  -----------
  Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"

This reverts commit 823e1b3818f9b10b824ddcd756983b6e2fa68730,
which introduces a regression running EDK2 guest firmware
under KVM:

error: kvm run failed Function not implemented
 PC=000000013f5a6208 X00=00000000404003c4 X01=000000000000003a
X02=0000000000000000 X03=00000000404003c4 X04=0000000000000000
X05=0000000096000046 X06=000000013d2ef270 X07=000000013e3d1710
X08=09010755ffaf8ba8 X09=ffaf8b9cfeeb5468 X10=feeb546409010756
X11=09010757ffaf8b90 X12=feeb50680903068b X13=090306a1ffaf8bc0
X14=0000000000000000 X15=0000000000000000 X16=000000013f872da0
X17=00000000ffffa6ab X18=0000000000000000 X19=000000013f5a92d0
X20=000000013f5a7a78 X21=000000000000003a X22=000000013f5a7ab2
X23=000000013f5a92e8 X24=000000013f631090 X25=0000000000000010
X26=0000000000000100 X27=000000013f89501b X28=000000013e3d14e0
X29=000000013e3d12a0 X30=000000013f5a2518  SP=000000013b7be0b0
PSTATE=404003c4 -Z-- EL1t

with
[ 3507.926571] kvm [35042]: load/store instruction decoding not implemented
in the host dmesg.

Revert the change for the moment until we can investigate the
cause of the regression.

Reported-by: Eric Auger <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a4e943a716d5fac923d82df3eabc65d1e3624019
      
https://github.com/qemu/qemu/commit/a4e943a716d5fac923d82df3eabc65d1e3624019
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M target/arm/helper.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Add helpers for FMLAL

Note that float16_to_float32 rightly squashes SNaN to QNaN.
But of course pickNaNMulAdd, for ARM, selects SNaNs first.
So we have to preserve SNaN long enough for the correct NaN
to be selected.  Thus float16_to_float32_by_bits.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0caa5af802ff622c854ff4ee2e2b8cdd135b4d73
      
https://github.com/qemu/qemu/commit/0caa5af802ff622c854ff4ee2e2b8cdd135b4d73
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement FMLAL and FMLSL for aarch64

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 87732318c5d68a366fc2d6fc394d9c20412099fa
      
https://github.com/qemu/qemu/commit/87732318c5d68a366fc2d6fc394d9c20412099fa
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Implement VFMAL and VFMSL for aarch32

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 991c05995a7bbafbebc1e4d405e947f2edcee063
      
https://github.com/qemu/qemu/commit/991c05995a7bbafbebc1e4d405e947f2edcee063
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Enable ARMv8.2-FHM for -cpu max

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1c9af3a9e05c1607a36df4943f8f5393d7621a91
      
https://github.com/qemu/qemu/commit/1c9af3a9e05c1607a36df4943f8f5393d7621a91
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9403bccfe3e271f04e12c8c64d306e0cff589009
      
https://github.com/qemu/qemu/commit/9403bccfe3e271f04e12c8c64d306e0cff589009
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-28 (Thu, 28 Feb 2019)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/arm/armsse.c
    M hw/misc/Makefile.objs
    A hw/misc/armsse-mhu.c
    M hw/misc/iotkit-sysctl.c
    M hw/misc/trace-events
    M include/hw/arm/armsse.h
    A include/hw/misc/armsse-mhu.h
    M include/hw/misc/iotkit-sysctl.h
    M linux-user/elfload.c
    M target/arm/arm-powerctl.c
    M target/arm/arm-powerctl.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/kvm32.c
    M target/arm/kvm64.c
    M target/arm/machine.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20190228-1' into staging

target-arm queue:
 * add MHU and dual-core support to Musca boards
 * refactor some VFP insns to be gated by ID registers
 * Revert "arm: Allow system registers for KVM guests to be changed by QEMU 
code"
 * Implement ARMv8.2-FHM extension
 * Advertise JSCVT via HWCAP for linux-user

# gpg: Signature made Thu 28 Feb 2019 11:06:55 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190228-1:
  linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT
  target/arm: Enable ARMv8.2-FHM for -cpu max
  target/arm: Implement VFMAL and VFMSL for aarch32
  target/arm: Implement FMLAL and FMLSL for aarch64
  target/arm: Add helpers for FMLAL
  Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
  target/arm: Gate "miscellaneous FP" insns by ID register field
  target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
  hw/arm/armsse: Unify init-svtor and cpuwait handling
  hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
  hw/arm/iotkit-sysctl: Add SSE-200 registers
  hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
  target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
  target/arm/cpu: Allow init-svtor property to be set after realize
  hw/arm/armsse: Wire up the MHUs
  hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/21ee7686d7b6...9403bccfe3e2