Index: dyngen.c
===================================================================
RCS file: /cvsroot/qemu/qemu/dyngen.c,v
retrieving revision 1.16
diff -u -p -r1.16 dyngen.c
--- dyngen.c	29 May 2003 20:05:18 -0000	1.16
+++ dyngen.c	1 Jun 2003 18:15:02 -0000
@@ -691,7 +691,7 @@ void gen_code(const char *name, host_ulo
 			case R_ALPHA_BRSGP:
 			    /* PC-relative jump. Tweak offset to skip the two instructions that try to
 			       set up the gp from the pv.  */
-			    fprintf(outfile, "    fix_bsr(gen_code_ptr + %ld, (uint8_t *) &%s - (gen_code_ptr + %ld) + 4);\n",
+			    fprintf(outfile, "    fix_bsr(gen_code_ptr + %ld, (uint8_t *) &%s - (gen_code_ptr + %ld + 4) + 8);\n",
 				    rel->r_offset - start_offset, sym_name, rel->r_offset - start_offset);
 			    break;
 			default:
Index: exec-i386.c
===================================================================
RCS file: /cvsroot/qemu/qemu/exec-i386.c,v
retrieving revision 1.26
diff -u -p -r1.26 exec-i386.c
--- exec-i386.c	29 May 2003 20:04:28 -0000	1.26
+++ exec-i386.c	1 Jun 2003 18:15:03 -0000
@@ -447,6 +447,34 @@ int cpu_x86_signal_handler(int host_sign
                              is_write, &uc->uc_sigmask);
 }
 
+#elif defined(__alpha__)
+
+int cpu_x86_signal_handler(int host_signum, struct siginfo *info, 
+                           void *puc)
+{
+    struct ucontext *uc = puc;
+    uint32_t *pc = uc->uc_mcontext.sc_pc;
+    uint32_t insn = *pc;
+    int is_write = 0;
+
+    switch (insn >> 26) {
+    case 0x0d: // stw
+    case 0x0e: // stb
+    case 0x0f: // stq_u
+    case 0x24: // stf
+    case 0x25: // stg
+    case 0x26: // sts
+    case 0x27: // stt
+    case 0x2c: // stl
+    case 0x2d: // stq
+    case 0x2e: // stl_c
+    case 0x2f: // stq_c
+	is_write = 1;
+    }
+
+    return handle_cpu_signal(pc, (unsigned long)info->si_addr, 
+                             is_write, &uc->uc_sigmask);
+}
 #else
 
 #error CPU specific signal handler needed
Index: exec-i386.h
===================================================================
RCS file: /cvsroot/qemu/qemu/exec-i386.h,v
retrieving revision 1.17
diff -u -p -r1.17 exec-i386.h
--- exec-i386.h	29 May 2003 20:04:28 -0000	1.17
+++ exec-i386.h	1 Jun 2003 18:15:03 -0000
@@ -124,6 +124,8 @@ register unsigned int A0 asm("$11");
 register unsigned int EAX asm("$12");
 register unsigned int ESP asm("$13");
 register unsigned int EBP asm("$14");
+/* Note $15 is the frame pointer, so anything in op-i386.c that would
+   require a frame pointer, like alloca, would probably loose.  */
 register struct CPUX86State *env asm("$15");
 #define reg_EAX
 #define reg_ESP
Index: exec.h
===================================================================
RCS file: /cvsroot/qemu/qemu/exec.h,v
retrieving revision 1.3
diff -u -p -r1.3 exec.h
--- exec.h	27 May 2003 23:29:24 -0000	1.3
+++ exec.h	1 Jun 2003 18:15:03 -0000
@@ -214,7 +214,7 @@ static inline int testandset (int *p)
 #endif
 
 #ifdef __alpha__
-int testandset (int *p)
+static inline int testandset (int *p)
 {
     int ret;
     unsigned long one;
Index: op-i386.c
===================================================================
RCS file: /cvsroot/qemu/qemu/op-i386.c,v
retrieving revision 1.31
diff -u -p -r1.31 op-i386.c
--- op-i386.c	29 May 2003 20:04:27 -0000	1.31
+++ op-i386.c	1 Jun 2003 18:15:05 -0000
@@ -1762,16 +1762,16 @@ typedef union {
     double d;
 #ifndef WORDS_BIGENDIAN
     struct {
-        unsigned long lower;
-        long upper;
+        uint32_t lower;
+        int32_t upper;
     } l;
 #else
     struct {
-        long upper;
-        unsigned long lower;
+        int32_t upper;
+        uint32_t lower;
     } l;
 #endif
-    long long ll;
+    int64_t ll;
 } CPU86_LDoubleU;
 
 /* the following deal with IEEE double-precision numbers */