--- qemu/hw/ne2000.c	Mon Jun 21 15:42:46 2004
+++ qemu/hw/ne2000.c	Fri Jul  9 20:57:32 2004
@@ -447,7 +447,7 @@
 #ifdef DEBUG_NE2000
     printf("NE2000: asic write val=0x%04x\n", val);
 #endif
-    if (s->rcnt == 0)
+    if ((s->rcnt == 0) || (s->rcnt == (uint16_t)-1))
 	    return;
     if (s->dcfg & 0x01) {
         /* 16 bit access */
@@ -463,7 +463,7 @@
     /* wrap */
     if (s->rsar == s->stop)
         s->rsar = s->start;
-    if (s->rcnt == 0) {
+    if ((s->rcnt == 0) || (s->rcnt == (uint16_t)-1)) {
         /* signal end of transfert */
         s->isr |= ENISR_RDC;
         ne2000_update_irq(s);
@@ -489,7 +489,7 @@
     /* wrap */
     if (s->rsar == s->stop)
         s->rsar = s->start;
-    if (s->rcnt == 0) {
+    if ((s->rcnt == 0) || (s->rcnt == (uint16_t)-1)) {
         /* signal end of transfert */
         s->isr |= ENISR_RDC;
         ne2000_update_irq(s);
@@ -507,7 +507,7 @@
 #ifdef DEBUG_NE2000
     printf("NE2000: asic writel val=0x%04x\n", val);
 #endif
-    if (s->rcnt == 0)
+    if ((s->rcnt == 0) || (s->rcnt == (uint16_t)-1))
 	    return;
     /* 32 bit access */
     ne2000_mem_writel(s, s->rsar, val);
@@ -516,7 +516,7 @@
     /* wrap */
     if (s->rsar == s->stop)
         s->rsar = s->start;
-    if (s->rcnt == 0) {
+    if ((s->rcnt == 0) || (s->rcnt == (uint16_t)-1)) {
         /* signal end of transfert */
         s->isr |= ENISR_RDC;
         ne2000_update_irq(s);
@@ -536,7 +536,7 @@
     /* wrap */
     if (s->rsar == s->stop)
         s->rsar = s->start;
-    if (s->rcnt == 0) {
+    if ((s->rcnt == 0) || (s->rcnt == (uint16_t)-1)) {
         /* signal end of transfert */
         s->isr |= ENISR_RDC;
         ne2000_update_irq(s);