Index: qemu-0.6.1/Makefile
===================================================================
--- qemu-0.6.1/Makefile	(.../qemu-0.6.1)	(revision 7)
+++ qemu-0.6.1/Makefile	(.../external/qemu-0.6.1)	(working copy)
@@ -1,6 +1,7 @@
 -include config-host.mak
 
-CFLAGS=-Wall -O2 -g -fno-strict-aliasing 
+VPATH = $(SRC_PATH)
+CFLAGS=-Wall -O2 -g -fno-strict-aliasing -I.
 ifdef CONFIG_DARWIN
 CFLAGS+= -mdynamic-no-pic
 endif
Index: qemu-0.6.1/Makefile.target
===================================================================
--- qemu-0.6.1/Makefile.target	(.../qemu-0.6.1)	(revision 7)
+++ qemu-0.6.1/Makefile.target	(.../external/qemu-0.6.1)	(working copy)
@@ -2,7 +2,7 @@
 
 TARGET_PATH=$(SRC_PATH)/target-$(TARGET_ARCH)
 VPATH=$(SRC_PATH):$(TARGET_PATH):$(SRC_PATH)/hw:$(SRC_PATH)/audio
-DEFINES=-I. -I$(TARGET_PATH) -I$(SRC_PATH)
+DEFINES=-I. -I.. -I$(TARGET_PATH) -I$(SRC_PATH)
 ifdef CONFIG_USER_ONLY
 VPATH+=:$(SRC_PATH)/linux-user
 DEFINES+=-I$(SRC_PATH)/linux-user -I$(SRC_PATH)/linux-user/$(TARGET_ARCH)
Index: qemu-0.6.1/hw/cuda.c
===================================================================
--- qemu-0.6.1/hw/cuda.c	(.../qemu-0.6.1)	(revision 7)
+++ qemu-0.6.1/hw/cuda.c	(.../external/qemu-0.6.1)	(working copy)
@@ -87,6 +87,9 @@
 #define CUDA_TIMER_FREQ (4700000 / 6)
 #define CUDA_ADB_POLL_FREQ 50
 
+/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
+#define RTC_OFFSET                      2082844800
+
 typedef struct CUDATimer {
     unsigned int latch;
     uint16_t counter_value; /* counter value at load time */
@@ -503,7 +506,7 @@
         break;
     case CUDA_GET_TIME:
         /* XXX: add time support ? */
-        ti = time(NULL);
+        ti = time(NULL) + RTC_OFFSET;
         obuf[0] = CUDA_PACKET;
         obuf[1] = 0;
         obuf[2] = 0;
@@ -522,6 +525,14 @@
         obuf[1] = 0;
         cuda_send_packet_to_host(s, obuf, 2);
         break;
+    case CUDA_POWERDOWN:
+        obuf[0] = CUDA_PACKET;
+        obuf[1] = 0;
+        cuda_send_packet_to_host(s, obuf, 2);
+	qemu_system_shutdown_request();
+	break;
+    case CUDA_MS_RESET:
+	
     default:
         break;
     }
Index: qemu-0.6.1/hw/openpic.c
===================================================================
--- qemu-0.6.1/hw/openpic.c	(.../qemu-0.6.1)	(revision 7)
+++ qemu-0.6.1/hw/openpic.c	(.../external/qemu-0.6.1)	(working copy)
@@ -345,7 +345,7 @@
     int i;
 
     opp->glbc = 0x80000000;
-    /* Initialise controler registers */
+    /* Initialise controller registers */
     opp->frep = ((EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID;
     opp->veni = VENI;
     opp->spve = 0x000000FF;
@@ -629,7 +629,7 @@
         break;
     case 0x10: /* TIBC */
 	if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
-	    (val & 0x800000000) == 0 &&
+	    (val & 0x80000000) == 0 &&
             (opp->timers[idx].tibc & 0x80000000) != 0)
 	    opp->timers[idx].ticc &= ~0x80000000;
 	opp->timers[idx].tibc = val;
Index: qemu-0.6.1/hw/ppc_prep.c
===================================================================
--- qemu-0.6.1/hw/ppc_prep.c	(.../qemu-0.6.1)	(revision 7)
+++ qemu-0.6.1/hw/ppc_prep.c	(.../external/qemu-0.6.1)	(working copy)
@@ -478,14 +478,21 @@
     cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
 
     isa_mem_base = 0xc0000000;
-    pci_bus = pci_prep_init();
+
+    if (pci_enabled)
+	pci_bus = pci_prep_init();
+    else
+	pci_bus = NULL;
+
     /* Register 64 KB of ISA IO space */
     PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
     cpu_register_physical_memory(0x80000000, 0x00010000, PPC_io_memory);
 
     /* init basic PC hardware */
-    vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, 
-                   vga_ram_size);
+    if (pci_enabled)
+	vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, 
+		       vga_ram_size);
+
     rtc_init(0x70, 8);
     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
     //    pic_init(openpic);
@@ -493,17 +500,26 @@
     //    pit = pit_init(0x40, 0);
 
     serial_init(0x3f8, 4, serial_hds[0]);
-    nb_nics1 = nb_nics;
-    if (nb_nics1 > NE2000_NB_MAX)
-        nb_nics1 = NE2000_NB_MAX;
-    for(i = 0; i < nb_nics1; i++) {
-        isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
-    }
 
-    for(i = 0; i < 2; i++) {
-        isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
-                     bs_table[2 * i], bs_table[2 * i + 1]);
-    }
+    if (pci_enabled) {
+        for(i = 0; i < nb_nics; i++) {
+            pci_ne2000_init(pci_bus, &nd_table[i]);
+        }
+        pci_ide_init(pci_bus, bs_table);
+    } else {
+        nb_nics1 = nb_nics;
+        if (nb_nics1 > NE2000_NB_MAX)
+            nb_nics1 = NE2000_NB_MAX;
+        for(i = 0; i < nb_nics1; i++) {
+            isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
+        }
+
+        for(i = 0; i < 2; i++) {
+            isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
+                         bs_table[2 * i], bs_table[2 * i + 1]);
+        }
+     }
+
     kbd_init();
     DMA_init(1);
     //    AUD_init();
Index: qemu-0.6.1/hw/pci.c
===================================================================
--- qemu-0.6.1/hw/pci.c	(.../qemu-0.6.1)	(revision 7)
+++ qemu-0.6.1/hw/pci.c	(.../external/qemu-0.6.1)	(working copy)
@@ -698,10 +698,25 @@
                                            PPC_PCIIO_write, s);
     cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
 
-    d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0,
-                            NULL, NULL);
+    /* PCI host bridge */ 
+    d = pci_register_device(s, "PREP Host Bridge - Motorola Raven", sizeof(PCIDevice), 
+                            0, NULL, NULL);
+    d->config[0x00] = 0x57; // vendor_id : Apple
+    d->config[0x01] = 0x10;
+    d->config[0x02] = 0x01; // device_id
+    d->config[0x03] = 0x48;
+    d->config[0x08] = 0x00; // revision
+    d->config[0x0A] = 0x00; // class_sub = pci host
+    d->config[0x0B] = 0x06; // class_base = PCI_bridge
+    d->config[0x0C] = 0x08; // cache_line_size
+    d->config[0x0D] = 0x10; // latency_timer
+    d->config[0x0E] = 0x00; // header_type
+    d->config[0x34] = 0x00; // capabilities_pointer
 
-    /* XXX: put correct IDs */
+    /* PCI to PCI bridge */
+    d = pci_register_device(s, "PREP PCI Bridge - Digital 21154", sizeof(PCIDevice),
+			    0xa0 << 3, NULL, NULL);
+    /* same values as PearPC - check this */
     d->config[0x00] = 0x11; // vendor_id
     d->config[0x01] = 0x10;
     d->config[0x02] = 0x26; // device_id
@@ -710,6 +725,7 @@
     d->config[0x0a] = 0x04; // class_sub = pci2pci
     d->config[0x0b] = 0x06; // class_base = PCI_bridge
     d->config[0x0e] = 0x01; // header_type
+
     return s;
 }
 
Index: qemu-0.6.1/vl.c
===================================================================
--- qemu-0.6.1/vl.c	(.../qemu-0.6.1)	(revision 7)
+++ qemu-0.6.1/vl.c	(.../external/qemu-0.6.1)	(working copy)
@@ -246,7 +246,7 @@
     for(i = start; i < start + length; i += size) {
         ioport_write_table[bsize][i] = func;
         if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
-            hw_error("register_ioport_read: invalid opaque");
+            hw_error("register_ioport_write: invalid opaque");
         ioport_opaque[i] = opaque;
     }
     return 0;