Re: [Qemu-devel] CP0 after reset bug (Was: Add MIPS ELF loader)

[Thiemo Seufer]

Alexander Voropay wrote:
[snip]
> Unfortunately, this code clears CU0  bits in the CP0(SR).
> It makes CP0 unusable for program and causes an exception 11 :
> Coprocessor Unusable on the next CP0 access.
> 
> The Qemu has a bug there. The "See MIPS Run" p.51 states:
> 
> CU0 - Coprocessor 0 usable; Set 1 to be able to use some nominally
> priveleged instructions in the user mode. You don't want to do this.
> The CPU control instructions encoded as coprocessor 0 type are
> always usable in kernel mode, regardless of the setting of this bit.
> 
> Qemu does simply check:
> ./target-mips/translate.c:1181
> ===================
>    if (!(ctx->CP0_Status & (1 << CP0St_CU0)) &&
>        !(ctx->hflags & MIPS_HFLAG_UM) &&
>        !(ctx->hflags & MIPS_HFLAG_ERL) &&
>        !(ctx->hflags & MIPS_HFLAG_EXL)) {
>        if (loglevel & CPU_LOG_TB_IN_ASM) {
>            fprintf(logfile, "CP0 is not usable\n");
>        }
>        generate_exception_err (ctx, EXCP_CpU, 0);
>        return;
> ===================
> 
> This check is not enought to emulate a Coprocessor Unusable
> situation on Reset (when CPU is in the kernel mode).

A patch which doesn't negate the HFLAGS_UM check fixes this and was
posted here a while ago.


Thiemo