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[Qemu-devel] Simulation of MIPS interrupts?
From: |
Dirk Behme |
Subject: |
[Qemu-devel] Simulation of MIPS interrupts? |
Date: |
Sun, 11 Jun 2006 19:03:46 +0200 |
User-agent: |
Mozilla Thunderbird 1.0.7 (X11/20050923) |
Hi,
looking in cpu_exec.c at cpu_exec() there are two code
blocks which call MIPS interrupt handling code (please see
below, (a) & (b) )
When is which block called?
I ask because a simple MIPS IRQ test doesn't work for me
like I would expect. I enable interrupts in status register.
Then, using code (b), system jumps to 0xbfc00380 like
expected. My expectation would be that I now can do
everything in ISR. As long as EXL is set it locks out
interrupts globally (like done in code (b) ). Even touching
HW and raising an additional IRQ in ISR shouldn't come
through until first called ISR exits with 'eret'. This is
what is checked in code (b): As long EXL ist set,
do_interrupt() isn't called again there.
But if additional IRQ is raised while in ISR, block (a) is
called (which does no checks like code (b)), system jumps to
0xbfc00380, executes ~7-8 assembly instructions and jumps
again to 0xbfc00380 via block (a). This results in an
infinite loop. eret of first ISR is never executed:
IRQ
exec (b)
jump 0xbfc00380
do sth, issue second IRQ
IRQ
exec (a)
jump 0xbfc00380
do ~7-8 assembly instructions
exec (a)
jump 0xbfc00380
do ~7-8 assembly instructions
exec (a)
jump 0xbfc00380
do ~7-8 assembly instructions
...
Best regards
Dirk
(a)
...
#elif defined(TARGET_MIPS)
do_interrupt(env);
#elif defined(TARGET_SPARC)
...
(b)
...
#elif defined(TARGET_MIPS)
if ((interrupt_request &
CPU_INTERRUPT_HARD) &&
(env->CP0_Status & (1 << CP0St_IE)) &&
(env->CP0_Status & env->CP0_Cause &
0x0000FF00) &&
!(env->hflags & MIPS_HFLAG_EXL) &&
!(env->hflags & MIPS_HFLAG_ERL) &&
!(env->hflags & MIPS_HFLAG_DM)) {
/* Raise it */
env->exception_index =
EXCP_EXT_INTERRUPT;
env->error_code = 0;
do_interrupt(env);
env->interrupt_request &=
~CPU_INTERRUPT_HARD;
...
- [Qemu-devel] Simulation of MIPS interrupts?,
Dirk Behme <=