Re: [Qemu-devel] Re: PATCH, RFC: Generic DMA framework

[Paul Brook]

> If this is the case, it means we don't need anything complicated. Devices
> map themselves straight into the system address space at the appropriate
> slot address (no plug-n-play to worry about), and device "DMA" goes via the
> IOMMU.

Further searching by google suggests I may be wrong.

The alternative is that the controller maps the 32-bit VA onto a device 
select+28-bit address, using some as-yet undiscovered mechanism.
There are then a couple of different options for how the CPU/memory bus is 
accessed:
a) The IOMMU is one or more slave devices, than feed the 28-bit address 
possibly plus a few other bits from the device ID into the translation table. 
This effectively allows you to map a proportion of the SBus 32-bit master VA 
space onto CPU address space via the IOMMU, and map the remainder onto 
devices on the same bus. For a system with <=8 slots per bus a fixed mapping 
using the first 2G as 256Mb for each slot and the top 2G for IOMMU is 
entirely feasible.
b) The 32-bit SBus VA is looked up directly into the IOMMU. Each IOMMU entry 
can refer to either a CPU address, or a device+28-bit address on the local 
SBUS.

Paul