Re: [Qemu-devel] [PATCH][MIPS] Fix [ls][wd][lr] instructions

[Aurelien Jarno]

Fabrice Bellard a écrit :
> Aurelien Jarno wrote:
>> Hi,
>>
>> As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr,
>> sdl and sdr instructions are not correctly implemented. In case of 
>> exception the BadVAddr register gets the aligned address instead of the
>> unaligned original address.
>>
>> In addition to that, the store instructions are generating the wrong
>> exception, AdEl instead of AdEs, because the current implementation 
>> first do a load.
>>
>> The patch below fixes that by accessing the bytes one by one, starting
>> by the unaligned original address.
>  > [...]
> 
> It would be a lot more efficient to add specific code in the MIPS 
> exception handling.
> 

That was the first approach I tried to follow, but it is not that easy.
Basically the solution is to add a new flag to CPUMIPSState to mark
instructions that need fix when an exception occurs and then fix the
exception type and address if needed.

Given those instructions are not used that often (unaligned memory
accesses have to be avoided), I am not sure it is worth adding too much
complexity in the mmu fault and exception handling code, which is used
by all instructions.

-- 
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