[Qemu-devel] about cache model in ARM emulation

[Boy Dfx]

Hello

 

I'm a newbie in the use of ARM simulators.

 

I got yesterday a question from my teacher and can't find the answer.

 

I would like to know weather QEMU simulates a cache miss (cache miss holds a penalty in terms of clock cycles or clock cycles counted) for an ARM-type core.

 

From what I can see instructions are loaded from memory without a clock cycle penalty, but I wanted to be sure.

 

 

Thanks

Gabi V.

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