Index: cpu-exec.c
===================================================================
RCS file: /sources/qemu/qemu/cpu-exec.c,v
retrieving revision 1.119
diff -u -d -d -p -r1.119 cpu-exec.c
--- cpu-exec.c	8 Oct 2007 13:16:13 -0000	1.119
+++ cpu-exec.c	9 Oct 2007 10:36:07 -0000
@@ -885,7 +885,7 @@ static inline int handle_cpu_signal(unsi
 
     /* see if it is an MMU fault */
     ret = cpu_x86_handle_mmu_fault(env, address, is_write,
-                                   ((env->hflags & HF_CPL_MASK) == 3), 0);
+                                   cpu_mem_index(env), 0);
     if (ret < 0)
         return 0; /* not an MMU fault */
     if (ret == 0)
@@ -1007,7 +1009,8 @@ static inline int handle_cpu_signal(unsi
     }
 
     /* see if it is an MMU fault */
-    ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
+    ret = cpu_ppc_handle_mmu_fault(env, address, is_write,
+                                   cpu_mem_index(env), 0);
     if (ret < 0)
         return 0; /* not an MMU fault */
     if (ret == 0)
@@ -1191,7 +1197,8 @@ static inline int handle_cpu_signal(unsi
     }
 
     /* see if it is an MMU fault */
-    ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0);
+    ret = cpu_alpha_handle_mmu_fault(env, address, is_write,
+                                     cpu_mem_index(env), 0);
     if (ret < 0)
         return 0; /* not an MMU fault */
     if (ret == 0)
Index: exec-all.h
===================================================================
RCS file: /sources/qemu/qemu/exec-all.h,v
retrieving revision 1.67
diff -u -d -d -p -r1.67 exec-all.h
--- exec-all.h	8 Oct 2007 13:16:14 -0000	1.67
+++ exec-all.h	9 Oct 2007 10:36:07 -0000
@@ -601,27 +606,7 @@ static inline target_ulong get_phys_addr
     int is_user, index, pd;
 
     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
-#if defined(TARGET_I386)
-    is_user = ((env->hflags & HF_CPL_MASK) == 3);
-#elif defined (TARGET_PPC)
-    is_user = msr_pr;
-#elif defined (TARGET_MIPS)
-    is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
-#elif defined (TARGET_SPARC)
-    is_user = (env->psrs == 0);
-#elif defined (TARGET_ARM)
-    is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
-#elif defined (TARGET_SH4)
-    is_user = ((env->sr & SR_MD) == 0);
-#elif defined (TARGET_ALPHA)
-    is_user = ((env->ps >> 3) & 3);
-#elif defined (TARGET_M68K)
-    is_user = ((env->sr & SR_S) == 0);
-#elif defined (TARGET_CRIS)
-    is_user = (0);
-#else
-#error unimplemented CPU
-#endif
+    is_user = cpu_mem_index(env);
     if (__builtin_expect(env->tlb_table[is_user][index].addr_code !=
                          (addr & TARGET_PAGE_MASK), 0)) {
         ldub_code(addr);
Index: softmmu_header.h
===================================================================
RCS file: /sources/qemu/qemu/softmmu_header.h,v
retrieving revision 1.17
diff -u -d -d -p -r1.17 softmmu_header.h
--- softmmu_header.h	8 Oct 2007 13:16:14 -0000	1.17
+++ softmmu_header.h	9 Oct 2007 10:36:07 -0000
@@ -51,54 +51,12 @@
 
 #elif ACCESS_TYPE == 2
 
-#ifdef TARGET_I386
-#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
-#elif defined (TARGET_PPC)
-#define CPU_MEM_INDEX (msr_pr)
-#elif defined (TARGET_MIPS)
-#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
-#elif defined (TARGET_SPARC)
-#define CPU_MEM_INDEX ((env->psrs) == 0)
-#elif defined (TARGET_ARM)
-#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
-#elif defined (TARGET_SH4)
-#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
-#elif defined (TARGET_ALPHA)
-#define CPU_MEM_INDEX ((env->ps >> 3) & 3)
-#elif defined (TARGET_M68K)
-#define CPU_MEM_INDEX ((env->sr & SR_S) == 0)
-#elif defined (TARGET_CRIS)
-/* CRIS FIXME: I guess we want to validate supervisor mode acceses here.  */
-#define CPU_MEM_INDEX (0)
-#else
-#error unsupported CPU
-#endif
+#define CPU_MEM_INDEX (cpu_mem_index(env))
 #define MMUSUFFIX _mmu
 
 #elif ACCESS_TYPE == 3
 
-#ifdef TARGET_I386
-#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
-#elif defined (TARGET_PPC)
-#define CPU_MEM_INDEX (msr_pr)
-#elif defined (TARGET_MIPS)
-#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
-#elif defined (TARGET_SPARC)
-#define CPU_MEM_INDEX ((env->psrs) == 0)
-#elif defined (TARGET_ARM)
-#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
-#elif defined (TARGET_SH4)
-#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
-#elif defined (TARGET_ALPHA)
-#define CPU_MEM_INDEX ((env->ps >> 3) & 3)
-#elif defined (TARGET_M68K)
-#define CPU_MEM_INDEX ((env->sr & SR_S) == 0)
-#elif defined (TARGET_CRIS)
-/* CRIS FIXME: I guess we want to validate supervisor mode acceses here.  */
-#define CPU_MEM_INDEX (0)
-#else
-#error unsupported CPU
-#endif
+#define CPU_MEM_INDEX (cpu_mem_index(env))
 #define MMUSUFFIX _cmmu
 
 #else
Index: target-alpha/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-alpha/cpu.h,v
retrieving revision 1.8
diff -u -d -d -p -r1.8 cpu.h
--- target-alpha/cpu.h	27 Sep 2007 16:44:31 -0000	1.8
+++ target-alpha/cpu.h	9 Oct 2007 10:36:07 -0000
@@ -302,6 +302,11 @@ struct CPUAlphaState {
 #define cpu_gen_code cpu_alpha_gen_code
 #define cpu_signal_handler cpu_alpha_signal_handler
 
+static inline int cpu_mem_index (CPUState *env)
+{
+    return (env->ps >> 3) & 3;
+}
+
 #include "cpu-all.h"
 
 enum {
Index: target-arm/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-arm/cpu.h,v
retrieving revision 1.34
diff -u -d -d -p -r1.34 cpu.h
--- target-arm/cpu.h	27 Sep 2007 16:44:31 -0000	1.34
+++ target-arm/cpu.h	9 Oct 2007 10:36:07 -0000
@@ -300,6 +300,11 @@ void cpu_arm_set_cp_io(CPUARMState *env,
 #define cpu_gen_code cpu_arm_gen_code
 #define cpu_signal_handler cpu_arm_signal_handler
 
+static inline int cpu_mem_index (CPUState *env)
+{
+    return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR;
+}
+
 #include "cpu-all.h"
 
 #endif
Index: target-cris/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-cris/cpu.h,v
retrieving revision 1.1
diff -u -d -d -p -r1.1 cpu.h
--- target-cris/cpu.h	8 Oct 2007 13:04:02 -0000	1.1
+++ target-cris/cpu.h	9 Oct 2007 10:36:07 -0000
@@ -229,6 +229,12 @@ void register_cris_insns (CPUCRISState *
 #define cpu_gen_code cpu_cris_gen_code
 #define cpu_signal_handler cpu_cris_signal_handler
 
+/* CRIS FIXME: I guess we want to validate supervisor mode acceses here.  */
+static inline int cpu_mem_index (CPUState *env)
+{
+    return 0;
+}
+
 #include "cpu-all.h"
 
 /* Register aliases.  */
Index: target-i386/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-i386/cpu.h,v
retrieving revision 1.50
diff -u -d -d -p -r1.50 cpu.h
--- target-i386/cpu.h	27 Sep 2007 16:44:31 -0000	1.50
+++ target-i386/cpu.h	9 Oct 2007 10:36:07 -0000
@@ -688,6 +688,11 @@ static inline int cpu_get_time_fast(void
 #define cpu_gen_code cpu_x86_gen_code
 #define cpu_signal_handler cpu_x86_signal_handler
 
+static inline int cpu_mem_index (CPUState *env)
+{
+    return (env->hflags & HF_CPL_MASK) == 3;
+}
+
 #include "cpu-all.h"
 
 #include "svm.h"
Index: target-m68k/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-m68k/cpu.h,v
retrieving revision 1.13
diff -u -d -d -p -r1.13 cpu.h
--- target-m68k/cpu.h	17 Sep 2007 08:09:53 -0000	1.13
+++ target-m68k/cpu.h	9 Oct 2007 10:36:07 -0000
@@ -223,6 +223,11 @@ void register_m68k_insns (CPUM68KState *
 #define cpu_gen_code cpu_m68k_gen_code
 #define cpu_signal_handler cpu_m68k_signal_handler
 
+static inline int cpu_mem_index (CPUState *env)
+{
+    return (env->sr & SR_S) == 0;
+}
+
 #include "cpu-all.h"
 
 #endif
Index: target-mips/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-mips/cpu.h,v
retrieving revision 1.47
diff -u -d -d -p -r1.47 cpu.h
--- target-mips/cpu.h	27 Sep 2007 16:44:31 -0000	1.47
+++ target-mips/cpu.h	9 Oct 2007 10:36:07 -0000
@@ -483,6 +483,11 @@ int cpu_mips_register (CPUMIPSState *env
 #define cpu_gen_code cpu_mips_gen_code
 #define cpu_signal_handler cpu_mips_signal_handler
 
+static inline int cpu_mem_index (CPUState *env)
+{
+    return (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
+}
+
 #include "cpu-all.h"
 
 /* Memory access type :
Index: target-ppc/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-ppc/cpu.h,v
retrieving revision 1.78
diff -u -d -d -p -r1.78 cpu.h
--- target-ppc/cpu.h	8 Oct 2007 02:58:07 -0000	1.78
+++ target-ppc/cpu.h	9 Oct 2007 10:36:07 -0000
@@ -698,6 +696,16 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, i
 #define cpu_gen_code cpu_ppc_gen_code
 #define cpu_signal_handler cpu_ppc_signal_handler
 
+static inline int cpu_mem_index (CPUState *env)
+{
+#if defined(TARGET_PPC64H)
+    if (msr_pr == 0 && msr_hv == 1)
+        return 2;
+    else
+#endif
+        return msr_pr;
+}
+
 #include "cpu-all.h"
 
 /*****************************************************************************/
Index: target-sh4/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-sh4/cpu.h,v
retrieving revision 1.10
diff -u -d -d -p -r1.10 cpu.h
--- target-sh4/cpu.h	16 Sep 2007 21:08:05 -0000	1.10
+++ target-sh4/cpu.h	9 Oct 2007 10:36:07 -0000
@@ -134,6 +134,11 @@ int cpu_sh4_signal_handler(int host_sign
 #define cpu_gen_code cpu_sh4_gen_code
 #define cpu_signal_handler cpu_sh4_signal_handler
 
+static inline int cpu_mem_index (CPUState *env)
+{
+    return (env->sr & SR_MD) == 0;
+}
+
 #include "cpu-all.h"
 
 /* Memory access type */
Index: target-sparc/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/cpu.h,v
retrieving revision 1.52
diff -u -d -d -p -r1.52 cpu.h
--- target-sparc/cpu.h	27 Sep 2007 16:44:32 -0000	1.52
+++ target-sparc/cpu.h	9 Oct 2007 10:36:07 -0000
@@ -316,6 +316,11 @@ void cpu_check_irqs(CPUSPARCState *env);
 #define cpu_gen_code cpu_sparc_gen_code
 #define cpu_signal_handler cpu_sparc_signal_handler
 
+static inline int cpu_mem_index (CPUState *env)
+{
+    return env->psrs == 0;
+}
+
 #include "cpu-all.h"
 
 #endif