[Qemu-devel] [PATCH] SH4, Add more float instructions.

[Takashi Yoshii]

Hi,
I found some instructions missing on SH4, and added some.
Graphics extentions(like sin/cos/sqrt/vector op) are still missing,
 but I believe no one need them, at least, so far.

"fneg" is implemented as 32bit op, according to the programming manual.
/yoshii

diff -u -p -r1.10 op.c
--- a/target-sh4/op.c   2 Dec 2007 06:18:24 -0000       1.10
+++ b/target-sh4/op.c   11 Dec 2007 17:24:31 -0000
@@ -797,6 +797,36 @@ void OPPROTO op_ftrc_DT(void)
     RETURN();
 }
 
+void OPPROTO op_fneg_frN(void)
+{
+    env->fregs[PARAM1] = float32_chs(env->fregs[PARAM1]);
+    RETURN();
+}
+
+void OPPROTO op_fabs_FT(void)
+{
+    FT0 = float32_abs(FT0);
+    RETURN();
+}
+
+void OPPROTO op_fabs_DT(void)
+{
+    DT0 = float64_abs(DT0);
+    RETURN();
+}
+
+void OPPROTO op_fcnvsd_DT(void)
+{
+    DT0 = float32_to_float64(env->fpul, &env->fp_status);
+    RETURN();
+}
+
+void OPPROTO op_fcnvds_DT(void)
+{
+    env->fpul = float64_to_float32(DT0, &env->fp_status);
+    RETURN();
+}
+
 void OPPROTO op_fmov_T0_frN(void)
 {
     *(unsigned int *)&env->fregs[PARAM1] = T0;
diff -u -p -r1.21 translate.c
--- a/target-sh4/translate.c    2 Dec 2007 06:10:04 -0000       1.21
+++ b/target-sh4/translate.c    11 Dec 2007 17:24:31 -0000
@@ -1123,6 +1123,23 @@ void _decode_opc(DisasContext * ctx)
            gen_op_ftrc_FT();
        }
        return;
+    case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
+       gen_op_fneg_frN(FREG(B11_8));
+       return;
+    case 0xf05d: /* fabs FRn/DRn */
+       if (ctx->fpscr & FPSCR_PR) {
+           if (ctx->opcode & 0x0100)
+               break; /* illegal instruction */
+           gen_op_fmov_drN_DT0(DREG(B11_8));
+           gen_op_fabs_DT();
+           gen_op_fmov_DT0_drN(DREG(B11_8));
+       }
+       else {
+           gen_op_fmov_frN_FT0(FREG(B11_8));
+           gen_op_fabs_FT();
+           gen_op_fmov_FT0_frN(FREG(B11_8));
+       }
+       return;
     case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
        if (!(ctx->fpscr & FPSCR_PR)) {
            gen_op_movl_imm_T0(0);
@@ -1137,6 +1154,14 @@ void _decode_opc(DisasContext * ctx)
            return;
        }
        break;
+    case 0xf0ad: /* cnvsd FPUL,DRn */
+       gen_op_fcnvsd_DT();
+       gen_op_fmov_DT0_drN(DREG(B11_8));
+       return;
+    case 0xf0bd: /* cnvds DRn,FPUL */
+       gen_op_fmov_drN_DT0(DREG(B11_8));
+       gen_op_fcnvds_DT();
+       return;
     }
 
     fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",