Re: [Qemu-devel] MIPS COP1X (and related) instructions

[Thiemo Seufer]

Richard Sandiford wrote:
> All MIPS COP1X instructions currently require the FPU to be in 64-bit
> mode.  My understanding is that this is too restrictive, and that the
> base conditions are different for different revisions of the ISA:
> 
>   MIPS IV:
>     COP1X instructions are available when the XX (CU3) bit of the
>     status register is set.  This bit can be set independently of
>     UX and FR, and controls the core MIPS IV instructions as well
>     as the FPU ones.

This part is, sadly, not fully correct. It depends on the CPU
implementation what effect, the CU3 bit has. IIRC it behaves on some
CPUs as you describe, while it is a nop on others.

(I don't know offhand which CPU did what there.)

>   Revision 1 of MIPS64:
>     COP1X instructions are available when 64-bit operations (as opposed
>     to 64-bit floating-point operations) are enabled.
> 
>   Revision 2 of MIPS32 and MIPS64:
>     COP1X instructions are available when a 64-bit FPU is present
>     (i.e. if FCR0.F64 is set).
> 
> The same conditions apply to some non-COP1X instructions too, such as
> RECIP.fmt and RSQRT.fmt.  Of course, some of the affected instructions
> really do require 64-bit mode, such as the paired-single ones.

This part is AFAIK correct.

> The attached patch is one attempt to fix this.  It's wrong if the
> description above is wrong.
> 
> Because the conditions are different for different ISAs, I thought it
> was worth adding a MIPS_HFLAG_* to say whether COP1X (and related)
> instructions are available.  This flag is directly associated with
> the nabla symbol in the MIPS32 and MIPS64 opcode tables.
> 
> Any instructions that requires FR to be set (as enforced by
> check_cp1_64bitmode) is also affected by the nabla behaviour,
> so I've made check_cp1_64bitmode depend on both flags.
> 
> I've added nabla checks for RECIP.S and RSQRT.S.  My understanding
> is that the *.D forms are unpredictable when FR is clear, and that
> QEMU generally uses check_cp1_64bitmode for such instructions.
> I've therefore replaced the existing "even register" checks with
> check_cp1_64bitmode, rather than add a separate nabla test.
> 
> I've replaced the single check_cp1_64bitmode calls in gen_flt3_ldst
> gen_flt3_arith with case-by-case checks.  I've also made CABS.[SD]
> use nabla checks instead of check_cp1_64bitmode and added nabla
> checks to BC1ANY[24].

Looks reasonable to me, apart from that one misassumption.


Thiemo