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[Qemu-devel] [PATCH 6/9] ICH-6 IDE controller
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 6/9] ICH-6 IDE controller |
Date: |
Tue, 08 Jan 2008 16:22:54 +0100 |
User-agent: |
Thunderbird 2.0.0.9 (X11/20070801) |
The oldest supported IDE controller in Mac OS X is the ICH6. This is an
incomplete implementation for that controller, that suffices for running
Mac OS X and worked with libata for me as well.
Index: qemu-snapshot-2008-01-08_05/hw/ide.c
===================================================================
--- qemu-snapshot-2008-01-08_05.orig/hw/ide.c
+++ qemu-snapshot-2008-01-08_05/hw/ide.c
@@ -386,6 +386,7 @@ typedef struct IDEState {
#define IDE_TYPE_PIIX3 0
#define IDE_TYPE_CMD646 1
#define IDE_TYPE_PIIX4 2
+#define IDE_TYPE_ICH6 3
/* CMD646 specific */
#define MRDMODE 0x71
@@ -2934,7 +2935,7 @@ static void piix3_reset(PCIIDEState *d)
{
uint8_t *pci_conf = d->dev.config;
- pci_conf[0x04] = 0x00;
+ pci_conf[0x04] = 0x01;
pci_conf[0x05] = 0x00;
pci_conf[0x06] = 0x80; /* FBC */
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
@@ -2961,11 +2962,68 @@ void pci_piix3_ide_init(PCIBus *bus, Blo
pci_conf[0x01] = 0x80;
pci_conf[0x02] = 0x10;
pci_conf[0x03] = 0x70;
+
+// ICH-6: 0x269e8086
+ pci_conf[0x00] = 0x86; // Intel
+ pci_conf[0x01] = 0x80;
+ //pci_conf[0x02] = 0x9e;// 11;
+ //pci_conf[0x03] = 0x26;//71;
+
+ pci_conf[0x09] = 0x80; // legacy ATA mode
+ pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
+ pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
+ pci_conf[0x0e] = 0x00; // header_type
+
+ pci_conf[0x40] = 0;
+ pci_conf[0x41] = 0xf0; // primary port enabled
+ pci_conf[0x42] = 0;
+ pci_conf[0x43] = 0x00; // secondary port disabled
+
+ piix3_reset(d);
+
+ pci_register_io_region((PCIDevice *)d, 4, 0x10,
+ PCI_ADDRESS_SPACE_IO, bmdma_map);
+
+ ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
+ ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
+ ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
+ ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
+
+ register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
+}
+
+/* hd_table must contain 4 block drivers */
+/* NOTE: for the ICH-6, the IRQs and IOports are hardcoded */
+void pci_ich6_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
+ qemu_irq *pic)
+{
+ PCIIDEState *d;
+ uint8_t *pci_conf;
+
+ /* register a function 1 of ICH-6 */
+ d = (PCIIDEState *)pci_register_device(bus, "ICH-6 IDE",
+ sizeof(PCIIDEState),
+ devfn,
+ NULL, NULL);
+ d->type = IDE_TYPE_ICH6;
+
+ pci_conf = d->dev.config;
+ pci_conf[0x00] = 0x86; // Intel
+ pci_conf[0x01] = 0x80;
+ pci_conf[0x02] = 0x9e;
+ pci_conf[0x03] = 0x26;
+
pci_conf[0x09] = 0x80; // legacy ATA mode
pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
pci_conf[0x0e] = 0x00; // header_type
+ pci_conf[0x40] = 0;
+ pci_conf[0x41] = 0xf0; // primary port enabled
+ pci_conf[0x42] = 0;
+ pci_conf[0x43] = 0x00; // secondary port disabled
+
+ //pci_conf[0x21] = 0xef; /* BMIBA: 20-23h */
piix3_reset(d);
pci_register_io_region((PCIDevice *)d, 4, 0x10,
Index: qemu-snapshot-2008-01-08_05/hw/pc.h
===================================================================
--- qemu-snapshot-2008-01-08_05.orig/hw/pc.h
+++ qemu-snapshot-2008-01-08_05/hw/pc.h
@@ -137,6 +137,8 @@ void pci_piix3_ide_init(PCIBus *bus, Blo
qemu_irq *pic);
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
qemu_irq *pic);
+void pci_ich6_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
+ qemu_irq *pic);
/* ne2000.c */
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