[Qemu-devel] [PATCH] Remove blank elements in tcg_target_reg_alloc_order[]

[Stuart Brady]

Hi,

tcg_target_reg_alloc_order[] contains blank elements, which default to
TCG_REG_EAX/TCG_REG_RAX on i386/x86_64, and TCG_REG_G0 on SPARC.  The
included patch removes these elements, and adds an ARRAY_SIZE macro to
osdep.h, which is then used to check the size of the array.

I'm not sure if the addition of ARRAY_SIZE is at all controversial.
I'll happily resubmit the patch with this removed if it's disliked.

Cheers,
-- 
Stuart Brady

diff -urp qemu-orig/osdep.h qemu-new/osdep.h
--- qemu-orig/osdep.h   2008-01-31 19:42:53.000000000 +0000
+++ qemu-new/osdep.h    2008-03-07 15:44:49.000000000 +0000
@@ -26,6 +26,10 @@
 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
 #endif
 
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
 #ifndef always_inline
 #if (__GNUC__ < 3) || defined(__APPLE__)
 #define always_inline inline
diff -urp qemu-orig/tcg/i386/tcg-target.c qemu-new/tcg/i386/tcg-target.c
--- qemu-orig/tcg/i386/tcg-target.c     2008-02-10 16:50:28.000000000 +0000
+++ qemu-new/tcg/i386/tcg-target.c      2008-03-07 15:26:47.000000000 +0000
@@ -32,7 +32,7 @@ const char *tcg_target_reg_names[TCG_TAR
     "%edi",
 };
 
-int tcg_target_reg_alloc_order[TCG_TARGET_NB_REGS] = {
+int tcg_target_reg_alloc_order[] = {
     TCG_REG_EAX,
     TCG_REG_EDX,
     TCG_REG_ECX,
diff -urp qemu-orig/tcg/sparc/tcg-target.c qemu-new/tcg/sparc/tcg-target.c
--- qemu-orig/tcg/sparc/tcg-target.c    2008-03-02 15:09:47.000000000 +0000
+++ qemu-new/tcg/sparc/tcg-target.c     2008-03-07 15:27:29.000000000 +0000
@@ -57,7 +57,7 @@ static const char * const tcg_target_reg
     "%i7",
 };
 
-static const int tcg_target_reg_alloc_order[TCG_TARGET_NB_REGS] = {
+static const int tcg_target_reg_alloc_order[] = {
     TCG_REG_L0,
     TCG_REG_L1,
     TCG_REG_L2,
diff -urp qemu-orig/tcg/tcg.c qemu-new/tcg/tcg.c
--- qemu-orig/tcg/tcg.c 2008-02-19 01:21:18.000000000 +0000
+++ qemu-new/tcg/tcg.c  2008-03-07 15:26:23.000000000 +0000
@@ -1212,14 +1212,14 @@ static int tcg_reg_alloc(TCGContext *s, 
     tcg_regset_andnot(reg_ct, reg1, reg2);
 
     /* first try free registers */
-    for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
+    for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
         reg = tcg_target_reg_alloc_order[i];
         if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == -1)
             return reg;
     }
 
     /* XXX: do better spill choice */
-    for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
+    for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
         reg = tcg_target_reg_alloc_order[i];
         if (tcg_regset_test_reg(reg_ct, reg)) {
             tcg_reg_free(s, reg);
diff -urp qemu-orig/tcg/x86_64/tcg-target.c qemu-new/tcg/x86_64/tcg-target.c
--- qemu-orig/tcg/x86_64/tcg-target.c   2008-03-02 15:09:47.000000000 +0000
+++ qemu-new/tcg/x86_64/tcg-target.c    2008-03-07 15:27:14.000000000 +0000
@@ -40,7 +40,7 @@ const char *tcg_target_reg_names[TCG_TAR
     "%r15",
 };
 
-int tcg_target_reg_alloc_order[TCG_TARGET_NB_REGS] = {
+int tcg_target_reg_alloc_order[] = {
     TCG_REG_RDI,
     TCG_REG_RSI,
     TCG_REG_RDX,