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[Qemu-devel] [4222] Remove an unused field and fix some non-code typos.
From: |
Andrzej Zaborowski |
Subject: |
[Qemu-devel] [4222] Remove an unused field and fix some non-code typos. |
Date: |
Sun, 20 Apr 2008 01:03:46 +0000 |
Revision: 4222
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4222
Author: balrog
Date: 2008-04-20 01:03:45 +0000 (Sun, 20 Apr 2008)
Log Message:
-----------
Remove an unused field and fix some non-code typos.
Modified Paths:
--------------
trunk/hw/twl92230.c
trunk/target-arm/helper.c
trunk/target-arm/translate.c
Modified: trunk/hw/twl92230.c
===================================================================
--- trunk/hw/twl92230.c 2008-04-20 00:58:01 UTC (rev 4221)
+++ trunk/hw/twl92230.c 2008-04-20 01:03:45 UTC (rev 4222)
@@ -62,7 +62,6 @@
int sec_offset;
int alm_sec;
int next_comp;
- struct tm *(*gettime)(const time_t *timep, struct tm *result);
} rtc;
qemu_irq handler[3];
qemu_irq *in;
Modified: trunk/target-arm/helper.c
===================================================================
--- trunk/target-arm/helper.c 2008-04-20 00:58:01 UTC (rev 4221)
+++ trunk/target-arm/helper.c 2008-04-20 01:03:45 UTC (rev 4222)
@@ -737,7 +737,7 @@
new_mode = ARM_CPU_MODE_SVC;
addr = 0x08;
mask = CPSR_I;
- /* The PC already points to the next instructon. */
+ /* The PC already points to the next instruction. */
offset = 0;
break;
case EXCP_BKPT:
@@ -870,7 +870,7 @@
type = (desc & 3);
domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
if (type == 0) {
- /* Secton translation fault. */
+ /* Section translation fault. */
code = 5;
goto do_fault;
}
@@ -961,7 +961,7 @@
desc = ldl_phys(table);
type = (desc & 3);
if (type == 0) {
- /* Secton translation fault. */
+ /* Section translation fault. */
code = 5;
domain = 0;
goto do_fault;
Modified: trunk/target-arm/translate.c
===================================================================
--- trunk/target-arm/translate.c 2008-04-20 00:58:01 UTC (rev 4221)
+++ trunk/target-arm/translate.c 2008-04-20 01:03:45 UTC (rev 4222)
@@ -2877,7 +2877,7 @@
tmp = load_cpu_field(vfp.xregs[rn]);
break;
case ARM_VFP_FPSCR:
- if (rd == 15) {
+ if (rd == 15) {
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
} else {
@@ -6887,7 +6887,7 @@
if (!(arm_feature(env, ARM_FEATURE_THUMB2)
|| arm_feature (env, ARM_FEATURE_M))) {
- /* Thumb-1 cores may need to tread bl and blx as a pair of
+ /* Thumb-1 cores may need to treat bl and blx as a pair of
16-bit instructions to get correct prefetch abort behavior. */
insn = insn_hw1;
if ((insn & (1 << 12)) == 0) {
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