[Qemu-devel] [4425] CRIS: Add support for the pseudo randomized set that the mmu provides with TLB refill faults .

[Edgar E. Iglesias]

Revision: 4425
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4425
Author:   edgar_igl
Date:     2008-05-11 14:28:14 +0000 (Sun, 11 May 2008)

Log Message:
-----------
CRIS: Add support for the pseudo randomized set that the mmu provides with TLB 
refill faults. This makes linux guests use the four way TLB set associativty.

Modified Paths:
--------------
    trunk/target-cris/cpu.h
    trunk/target-cris/mmu.c

Modified: trunk/target-cris/cpu.h
===================================================================
--- trunk/target-cris/cpu.h     2008-05-11 12:22:01 UTC (rev 4424)
+++ trunk/target-cris/cpu.h     2008-05-11 14:28:14 UTC (rev 4425)
@@ -153,6 +153,11 @@
        */
        uint32_t sregs[4][16];
 
+       /* Linear feedback shift reg in the mmu. Used to provide pseudo
+          randomness for the 'hint' the mmu gives to sw for chosing valid
+          sets on TLB refills.  */
+       uint32_t mmu_rand_lfsr;
+
        /*
         * We just store the stores to the tlbset here for later evaluation
         * when the hw needs access to them.

Modified: trunk/target-cris/mmu.c
===================================================================
--- trunk/target-cris/mmu.c     2008-05-11 12:22:01 UTC (rev 4424)
+++ trunk/target-cris/mmu.c     2008-05-11 14:28:14 UTC (rev 4425)
@@ -32,6 +32,24 @@
 
 #define D(x)
 
+void cris_mmu_init(CPUState *env)
+{
+       env->mmu_rand_lfsr = 0xcccc;
+}
+
+#define SR_POLYNOM 0x8805
+static inline unsigned int compute_polynom(unsigned int sr)
+{
+       unsigned int i;
+       unsigned int f;
+
+       f = 0;
+       for (i = 0; i < 16; i++)
+               f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
+
+       return f;
+}
+
 static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
 {
        return (rw_gc_cfg & 12) != 0;
@@ -152,11 +170,14 @@
                hi = env->tlbsets[mmu][set][idx].hi;
 
                tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
+               tlb_pid = EXTRACT_FIELD(hi, 0, 7);
                tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
+               tlb_g  = EXTRACT_FIELD(lo, 4, 4);
 
                D(printf("TLB[%d][%d] v=%x vpage=%x -> pfn=%x lo=%x hi=%x\n", 
                                i, idx, tlb_vpn, vpage, tlb_pfn, lo, hi));
-               if (tlb_vpn == vpage) {
+               if ((tlb_g || (tlb_pid == (env->pregs[PR_PID] & 0xff)))
+                   && tlb_vpn == vpage) {
                        match = 1;
                        break;
                }
@@ -169,9 +190,7 @@
                cfg_x  = EXTRACT_FIELD(r_cfg, 17, 17);
                cfg_v  = EXTRACT_FIELD(r_cfg, 16, 16);
 
-               tlb_pid = EXTRACT_FIELD(hi, 0, 7);
                tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
-               tlb_g  = EXTRACT_FIELD(lo, 4, 4);
                tlb_v = EXTRACT_FIELD(lo, 3, 3);
                tlb_k = EXTRACT_FIELD(lo, 2, 2);
                tlb_w = EXTRACT_FIELD(lo, 1, 1);
@@ -187,13 +206,7 @@
                set_exception_vector(0x0a, d_mmu_access);
                set_exception_vector(0x0b, d_mmu_write);
                */
-               if (!tlb_g
-                   && tlb_pid != (env->pregs[PR_PID] & 0xff)) {
-                       D(printf ("tlb: wrong pid %x %x pc=%x\n", 
-                                tlb_pid, env->pregs[PR_PID], env->pc));
-                       match = 0;
-                       res->bf_vec = vect_base;
-               } else if (cfg_k && tlb_k && usermode) {
+               if (cfg_k && tlb_k && usermode) {
                        D(printf ("tlb: kernel protected %x lo=%x pc=%x\n", 
                                  vaddr, lo, env->pc));
                        match = 0;
@@ -229,17 +242,27 @@
 
                env->sregs[SFR_RW_MM_TLB_HI] = hi;
                env->sregs[SFR_RW_MM_TLB_LO] = lo;
+       } else {
+               /* If refill, provide a randomized set.  */
+               set = env->mmu_rand_lfsr & 3;
        }
 
        if (!match) {
-               /* miss.  */
+               unsigned int f;
+
+               /* Update lfsr at every fault.  */
+               f = compute_polynom(env->mmu_rand_lfsr);
+               env->mmu_rand_lfsr >>= 1;
+               env->mmu_rand_lfsr |= (f << 15);
+               env->mmu_rand_lfsr &= 0xffff;
+               
+               /* Compute index.  */
                idx = vpage & 15;
-               set = 0;
 
                /* Update RW_MM_TLB_SEL.  */
                env->sregs[SFR_RW_MM_TLB_SEL] = 0;
                set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
-               set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 5);
+               set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
 
                /* Update RW_MM_CAUSE.  */
                set_field(&r_cause, rwcause, 8, 2);