[Qemu-devel] [4467] Generate better code for Sparc32 shifts

[Blue Swirl]

Revision: 4467
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=4467
Author:   blueswir1
Date:     2008-05-17 09:43:12 +0000 (Sat, 17 May 2008)

Log Message:
-----------
Generate better code for Sparc32 shifts

Modified Paths:
--------------
    trunk/target-sparc/translate.c

Modified: trunk/target-sparc/translate.c
===================================================================
--- trunk/target-sparc/translate.c      2008-05-17 09:41:14 UTC (rev 4466)
+++ trunk/target-sparc/translate.c      2008-05-17 09:43:12 UTC (rev 4467)
@@ -3008,18 +3008,33 @@
                         break;
 #ifndef TARGET_SPARC64
                     case 0x25:  /* sll */
-                        tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
-                        tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
+                        if (IS_IMM) { /* immediate */
+                            rs2 = GET_FIELDs(insn, 20, 31);
+                            tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
+                        } else { /* register */
+                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
+                            tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
+                        }
                         gen_movl_TN_reg(rd, cpu_dst);
                         break;
                     case 0x26:  /* srl */
-                        tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
-                        tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
+                        if (IS_IMM) { /* immediate */
+                            rs2 = GET_FIELDs(insn, 20, 31);
+                            tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
+                        } else { /* register */
+                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
+                            tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
+                        }
                         gen_movl_TN_reg(rd, cpu_dst);
                         break;
                     case 0x27:  /* sra */
-                        tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
-                        tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
+                        if (IS_IMM) { /* immediate */
+                            rs2 = GET_FIELDs(insn, 20, 31);
+                            tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
+                        } else { /* register */
+                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
+                            tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
+                        }
                         gen_movl_TN_reg(rd, cpu_dst);
                         break;
 #endif