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Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)
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From: |
Jamie Lokier |
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Subject: |
Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system) |
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Date: |
Thu, 22 May 2008 23:04:27 +0100 |
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User-agent: |
Mutt/1.5.13 (2006-08-11) |
Thiemo Seufer wrote:
> > Yes, they do use the noraml MIPS ISA. It is a MIPS64r2 part.
>
> AFAIU they invented a mode in their core which replaces (d)lwl/(d)lwr
> with different instructions for unaligned load/stores. :-(
The Alteon Tigon 2 gigabit ethernet processor did something similar,
except it wasn't a mode but fixed.
The documentation said it was because those particular instructions
are covered by a patent, so they couldn't implement them.
-- Jaie
Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system), M. Warner Losh, 2008/05/22