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Re: [Qemu-devel] Threading Qemu
From: |
Jamie Lokier |
Subject: |
Re: [Qemu-devel] Threading Qemu |
Date: |
Wed, 28 May 2008 13:39:59 +0100 |
User-agent: |
Mutt/1.5.13 (2006-08-11) |
Fabrice Bellard wrote:
> I confirm, the general case is quite complicated. It is simpler to begin
> with an implementation where the host and guest CPUs have the same
> memory ordering constraints (e.g. x86 on x86 case).
I have just realised it is not _always_ correct even for x86 on x86,
for some flavours of x86 host CPU.
Qemu emulates a standard x86 with writes fully ordered. Guest code
will assume that.
But a few types of x86 host don't fully order writes. See
CONFIG_X86_OOSTORE and CONFIG_X86_PPRO_FENCE in Linux kernels - look
in linux/arch/x86/Kconfig.cpu.
On those, running multiple target CPUs as host threads on a
multiprocessor host may not be correct.
I'm not sure if the "sfence" instruction means this could apply to
some modern, mainstream x86 hosts too.
-- Jamie