[Qemu-devel] Patch: fix encoding of efsctsiz (powerpc spe)

[Tristan Gingold]

Hi,

according to the e500 core RM, the encoding of efsctsiz and efsctuiz  
are:

evfsctsiz 0 0 0 1 0 0 rD /// rB 0 1 0 1 0 0 1 1 0 1 0 EVX evfsctsiz
evfsctuiz 0 0 0 1 0 0 rD /// rB 0 1 0 1 0 0 1 1 0 0 0 EVX evfsctuiz

they do not differ by the Rc bit but by the opc2 field.
This patch fixes this bug.

Tristan.


--- target-ppc/translate.c      (revision 126210)
+++ target-ppc/translate.c      (working copy)
@@ -5988,7 +5988,8 @@
 GEN_SPE(efscfuf,        efscfsf,       0x09, 0x0B, 0x00180000,  
PPC_SPEFPU); //
 GEN_SPE(efsctui,        efsctsi,       0x0A, 0x0B, 0x00180000,  
PPC_SPEFPU); //
 GEN_SPE(efsctuf,        efsctsf,       0x0B, 0x0B, 0x00180000,  
PPC_SPEFPU); //
-GEN_SPE(efsctuiz,       efsctsiz,      0x0C, 0x0B, 0x00180000,  
PPC_SPEFPU); //
+GEN_SPE(efsctuiz,       speundef,      0x0C, 0x0B, 0x00180000,  
PPC_SPEFPU); //
+GEN_SPE(efsctsiz,       speundef,      0x0D, 0x0B, 0x00180000,  
PPC_SPEFPU); //
 GEN_SPE(efststgt,       efststlt,      0x0E, 0x0B, 0x00600000,  
PPC_SPEFPU); //
 GEN_SPE(efststeq,       speundef,      0x0F, 0x0B, 0x00600000,  
PPC_SPEFPU); //