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Re: [Qemu-devel] Sparc32: Mask writes to the WIM register
From: |
Luis Pureza |
Subject: |
Re: [Qemu-devel] Sparc32: Mask writes to the WIM register |
Date: |
Wed, 20 Aug 2008 08:48:42 +0100 |
OK, the following patch works for me:
---
target-sparc/translate.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 8286d36..02e497f 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -73,6 +73,7 @@ typedef struct DisasContext {
struct TranslationBlock *tb;
uint32_t features;
int extra_cpu_cycles;
+ uint32_t wim_mask;
} DisasContext;
// This function uses non-native bit order
@@ -3485,6 +3486,7 @@ static void disas_sparc_insn(DisasContext * dc)
}
#else
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
+ tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
dc->wim_mask);
tcg_gen_st_i32(cpu_tmp32, cpu_env,
offsetof(CPUSPARCState, wim));
#endif
@@ -4848,6 +4850,11 @@ static inline void
gen_intermediate_code_internal(TranslationBlock * tb,
#ifdef TARGET_SPARC64
dc->address_mask_32bit = env->pstate & PS_AM;
#endif
+ if (env->nwindows == 32) {
+ dc->wim_mask = 0xFFFFFFFF;
+ } else {
+ dc->wim_mask = (1 << env->nwindows) - 1;
+ }
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);