[Qemu-devel] Re: [Bochs-developers] BIOS, ACPI, CMOS and Windows EvenID: 4

[Sebastian Herbszt]

Gleb Natapov wrote:
> So is something like this should be OK:
>
>
> Index: acpi-dsdt.dsl
> ===================================================================
> RCS file: /cvsroot/bochs/bochs/bios/acpi-dsdt.dsl,v
> retrieving revision 1.3
> diff -u -r1.3 acpi-dsdt.dsl
> --- acpi-dsdt.dsl 26 Jan 2008 09:15:27 -0000 1.3
> +++ acpi-dsdt.dsl 21 Aug 2008 14:13:35 -0000
> @@ -27,20 +27,6 @@
> {
>     Scope (\)
>     {
> -        /* CMOS memory access */
> -        OperationRegion (CMS, SystemIO, 0x70, 0x02)
> -        Field (CMS, ByteAcc, NoLock, Preserve)
> -        {
> -            CMSI,   8,
> -            CMSD,   8
> -        }
> -        Method (CMRD, 1, NotSerialized)
> -        {
> -            Store (Arg0, CMSI)
> -            Store (CMSD, Local0)
> -            Return (Local0)
> -        }
> -
>         /* Debug Output */
>         OperationRegion (DBG, SystemIO, 0xb044, 0x04)
>         Field (DBG, DWordAcc, NoLock, Preserve)
> @@ -56,6 +42,12 @@
>             Name (_HID, EisaId ("PNP0A03"))
>             Name (_ADR, 0x00)
>             Name (_UID, 1)
> +            OperationRegion (I440, PCI_Config, 0x60, 0x02)
> +            Field (I440, ByteAcc, NoLock, Preserve)
> +            {
> +                 CM34,   8,
> +                 CM35,   8,
> +            }
>             Name(_PRT, Package() {
>                 /* PCI IRQ routing table, example from ACPI 2.0a specification,
>                    section 6.2.8.1 */
> @@ -149,7 +141,9 @@
>                 CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._MAX, PMAX)
>                 CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._LEN, PLEN)
>                 /* compute available RAM */
> -                Add(CMRD(0x34), ShiftLeft(CMRD(0x35), 8), Local0)
> +                Store(CM34, Local1)
> +                Store(CM35, Local2)
> +                Add(Local1, ShiftLeft(Local2, 8), Local0)
>                 ShiftLeft(Local0, 16, Local0)
>                 Add(Local0, 0x1000000, Local0)
>                 /* update field of last region */

I just noticed the original code might not compute PMIN correctly for low memory
configurations. If ram size is below 16MB CMOS registers 0x34 and 0x35 are set 
to
zero. In this case PMIN is still computed by adding 16MB. This might be 
intended tho.

> Index: rombios32.c
> ===================================================================
> RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
> retrieving revision 1.29
> diff -u -r1.29 rombios32.c
> --- rombios32.c 30 Jul 2008 15:13:40 -0000 1.29
> +++ rombios32.c 21 Aug 2008 14:13:36 -0000
> @@ -677,6 +677,8 @@
>                 elcr[0], elcr[1]);
>     } else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == 
> PCI_DEVICE_ID_INTEL_82441) {
>         /* i440 PCI bridge */
> +        pci_config_writeb(d, 0x60, cmos_readb(0x34));
> +        pci_config_writeb(d, 0x61, cmos_readb(0x35));
>         bios_shadow_init(d);
>     }
> }

I am not sure writing arbitrary values to those registers is such a good idea. 
Some OS,
driver or application could rely on the information stored there.

The 440FX PMC supports up to 1GB of memory. Top of memory is the value read from
DRB7 multiplied by 8MB, so the maximal DRB7 value is 0x80.
VMware and Virtual PC emulate the 440BX/ZX/DX PMC. The 440BX supports up
to 1GB and the 440ZX up to 256MB of memory (i could not find any specs on the 
DX).
I think both products support memory configurations above 1GB, so it might be 
useful to
know what they program those DRBx registers to.

It would also be possible to program those DRBx registers correctly up to memory
value of 1GB (or 2GB by using the info from the 440GX) and compute the pci hole 
properly,
then just fall back to 0xe0000000 if the memory size does exceed 1GB.
Hard coding the hole start to 0xe0000000, like you did in your first patch, 
looks like the
easiest solution tho.

- Sebastian