[Qemu-devel] [5098] SH4: Convert immediate loads to TCG

[Aurelien Jarno]

Revision: 5098
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5098
Author:   aurel32
Date:     2008-08-28 21:02:19 +0000 (Thu, 28 Aug 2008)

Log Message:
-----------
SH4: Convert immediate loads to TCG

Signed-off-by: Aurelien Jarno <address@hidden>

Modified Paths:
--------------
    trunk/target-sh4/op.c
    trunk/target-sh4/translate.c

Modified: trunk/target-sh4/op.c
===================================================================
--- trunk/target-sh4/op.c       2008-08-28 21:02:08 UTC (rev 5097)
+++ trunk/target-sh4/op.c       2008-08-28 21:02:19 UTC (rev 5098)
@@ -37,18 +37,6 @@
        clr_t();
 }
 
-void OPPROTO op_movl_imm_T0(void)
-{
-    T0 = (uint32_t) PARAM1;
-    RETURN();
-}
-
-void OPPROTO op_movl_imm_T1(void)
-{
-    T1 = (uint32_t) PARAM1;
-    RETURN();
-}
-
 void OPPROTO op_cmp_eq_imm_T0(void)
 {
     cond_t((int32_t) T0 == (int32_t) PARAM1);

Modified: trunk/target-sh4/translate.c
===================================================================
--- trunk/target-sh4/translate.c        2008-08-28 21:02:08 UTC (rev 5097)
+++ trunk/target-sh4/translate.c        2008-08-28 21:02:19 UTC (rev 5098)
@@ -337,12 +337,12 @@
        gen_op_movl_imm_rN(B7_0s, REG(B11_8));
        return;
     case 0x9000:               /* mov.w @(disp,PC),Rn */
-       gen_op_movl_imm_T0(ctx->pc + 4 + B7_0 * 2);
+       tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
        gen_op_ldw_T0_T0(ctx);
        gen_op_movl_T0_rN(REG(B11_8));
        return;
     case 0xd000:               /* mov.l @(disp,PC),Rn */
-       gen_op_movl_imm_T0((ctx->pc + 4 + B7_0 * 4) & ~3);
+       tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
        gen_op_ldl_T0_T0(ctx);
        gen_op_movl_T0_rN(REG(B11_8));
        return;
@@ -1181,14 +1181,14 @@
        break;
     case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
        if (!(ctx->fpscr & FPSCR_PR)) {
-           gen_op_movl_imm_T0(0);
+           tcg_gen_movi_tl(cpu_T[0], 0);
            gen_op_fmov_T0_frN(FREG(B11_8));
            return;
        }
        break;
     case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
        if (!(ctx->fpscr & FPSCR_PR)) {
-           gen_op_movl_imm_T0(0x3f800000);
+           tcg_gen_movi_tl(cpu_T[0], 0x3f800000);
            gen_op_fmov_T0_frN(FREG(B11_8));
            return;
        }