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[Qemu-devel] [PATCH][ppc] reorganize register set for SPE + TCG
|
From: |
Nathan Froyd |
|
Subject: |
[Qemu-devel] [PATCH][ppc] reorganize register set for SPE + TCG |
|
Date: |
Wed, 15 Oct 2008 07:22:38 -0700 |
|
User-agent: |
Mutt/1.5.13 (2006-08-11) |
The (large, invasive) patch below is a preparation patch for converting
(most) SPE instructions to use TCG. The rationale is that your ordinary
SPE instruction deals with three 64-bit quantaties (and a potential
64-bit accumulator). In the current implementation, it's extremely
laborious/difficult to pass those 64-bit quantaties to helpers, since
the high/low words for SPE registers are not contiguous in the
environment. (TCG helpers for SPE instructions are not yet implemented,
but they will be necessary as part of the total conversion to TCG.)
The only way I see to do it is to pass six things--the 32-bit argument
words and two pointers to the result words--and deal with high/low words
separately (and two more to account for potential accumulators). Except
that TCG currently doesn't support six-argument (eight-argument)
helpers--at least not as far as I can see.
I suppose TCG could be changed to accommodate eight-argument helpers,
but I know the PPC target a bit better than I know TCG, so this is the
way I decided to go for now. Forcing that complexity into TCG for one
target's purposes also doesn't seem like the greatest idea. The
TARGET_PPC64 cases would have to be implemented separately as well (or
require changes which are similar to the ones I have made), which gets
tedious to read and write after a while.
The main idea of the patch is simple enough: the GPRs in the environment
are now always 64-bit quantities and we access the relevant 32-bit
halves or 64-bit whole as necessary. Most of the bulk of the patch
comes from env->gpr[i] not being an integer type anymore; I introduced a
helper macro to reference the 64-bit whole or the appropriate 32-bit
half instead. Marshaling 64-bit quantities is extremely easy now that
the high/low words for SPE registers are contiguous in the environment;
we can just pass a pointer to the relevant location. Implementing a
normal SPE instruction (one result, two arguments, and optional
accumulator) then requires just four pointer arguments...a perfect fit
for TCG.
Other (potential) benefits of this change include the ability to
implement certain 2-element vector instructions directly in TCG without
helpers and general elimination of TARGET_PPC64 #ifs. I included a
small bugfix to the way Altivec registers were implemented in the patch;
if the patch proves to be too invasive, then I can break that out and
submit that separately.
I don't know if the introduction of so many tcg_global_mem_new's will be
detrimental to TCG's performance, but I will leave comment on that to
somebody more expert than I.
-Nathan
diff -r 5ed4e3fd0fe7 -r 8a7ea9ce5335 gdbstub.c
--- a/gdbstub.c Tue Oct 14 15:23:35 2008 -0400
+++ b/gdbstub.c Wed Oct 15 08:45:29 2008 -0400
@@ -426,7 +426,7 @@
{
if (n < 32) {
/* gprs */
- GET_REGL(env->gpr[n]);
+ GET_REGL(GPR(env, n));
} else if (n < 64) {
/* fprs */
stfq_p(mem_buf, env->fpr[n]);
@@ -456,7 +456,7 @@
{
if (n < 32) {
/* gprs */
- env->gpr[n] = ldtul_p(mem_buf);
+ GPR(env, n) = ldtul_p(mem_buf);
return sizeof(target_ulong);
} else if (n < 64) {
/* fprs */
diff -r 5ed4e3fd0fe7 -r 8a7ea9ce5335 linux-user/main.c
--- a/linux-user/main.c Tue Oct 14 15:23:35 2008 -0400
+++ b/linux-user/main.c Wed Oct 15 08:45:29 2008 -0400
@@ -1439,18 +1439,18 @@
* in syscalls.
*/
#if 0
- printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
- env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
+ printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", GPR(env, 0),
+ GPR(env, 3), GPR(env, 4), GPR(env, 5), GPR(env, 6));
#endif
env->crf[0] &= ~0x1;
- ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
- env->gpr[5], env->gpr[6], env->gpr[7],
- env->gpr[8]);
+ ret = do_syscall(env, GPR(env, 0), GPR(env, 3), GPR(env, 4),
+ GPR(env, 5), GPR(env, 6), GPR(env, 7),
+ GPR(env, 8));
if (ret > (uint32_t)(-515)) {
env->crf[0] |= 0x1;
ret = -ret;
}
- env->gpr[3] = ret;
+ GPR(env, 3) = ret;
#if 0
printf("syscall returned 0x%08x (%d)\n", ret, ret);
#endif
@@ -2557,7 +2557,7 @@
#endif
env->nip = regs->nip;
for(i = 0; i < 32; i++) {
- env->gpr[i] = regs->gpr[i];
+ GPR(env, i) = regs->gpr[i];
}
}
#elif defined(TARGET_M68K)
diff -r 5ed4e3fd0fe7 -r 8a7ea9ce5335 linux-user/ppc/target_signal.h
--- a/linux-user/ppc/target_signal.h Tue Oct 14 15:23:35 2008 -0400
+++ b/linux-user/ppc/target_signal.h Wed Oct 15 08:45:29 2008 -0400
@@ -23,7 +23,7 @@
static inline abi_ulong get_sp_from_cpustate(CPUPPCState *state)
{
- return state->gpr[1];
+ return GPR(state, 1);
}
#endif /* TARGET_SIGNAL_H */
diff -r 5ed4e3fd0fe7 -r 8a7ea9ce5335 target-ppc/cpu.h
--- a/target-ppc/cpu.h Tue Oct 14 15:23:35 2008 -0400
+++ b/target-ppc/cpu.h Wed Oct 15 08:45:29 2008 -0400
@@ -290,6 +290,7 @@
typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_spr_t ppc_spr_t;
typedef struct ppc_dcr_t ppc_dcr_t;
+typedef union ppc_reg_t ppc_reg_t;
typedef union ppc_avr_t ppc_avr_t;
typedef union ppc_tlb_t ppc_tlb_t;
@@ -304,6 +305,12 @@
void (*hea_write)(void *opaque, int spr_num);
#endif
const char *name;
+};
+
+/* GPRs */
+union ppc_reg_t {
+ uint32_t u32[2];
+ uint64_t u64;
};
/* Altivec registers (128 bits) */
@@ -529,22 +536,19 @@
/* First are the most commonly used resources
* during translated code execution
*/
-#if TARGET_LONG_BITS > HOST_LONG_BITS
- target_ulong t0, t1, t2;
-#endif
-#if !defined(TARGET_PPC64)
- /* temporary fixed-point registers
- * used to emulate 64 bits registers on 32 bits targets
- */
- uint64_t t0_64, t1_64, t2_64;
-#endif
+ ppc_reg_t t0, t1, t2;
ppc_avr_t avr0, avr1, avr2;
/* general purpose registers */
- target_ulong gpr[32];
-#if !defined(TARGET_PPC64)
- /* Storage for GPR MSB, used by the SPE extension */
- target_ulong gprh[32];
+ ppc_reg_t gpr[32];
+#if defined(TARGET_PPC64)
+#define GPR(env, i) env->gpr[i].u64
+#else
+#if defined(WORDS_BIGENDIAN)
+#define GPR(env, i) env->gpr[i].u32[1]
+#else
+#define GPR(env, i) env->gpr[i].u32[0]
+#endif
#endif
/* LR */
target_ulong lr;
@@ -777,14 +781,12 @@
{
uint64_t gprv;
- gprv = env->gpr[gprn];
+ gprv = GPR(env, gprn);
#if !defined(TARGET_PPC64)
if (env->flags & POWERPC_FLAG_SPE) {
- /* If the CPU implements the SPE extension, we have to get the
- * high bits of the GPR from the gprh storage area
- */
- gprv &= 0xFFFFFFFFULL;
- gprv |= (uint64_t)env->gprh[gprn] << 32;
+ /* If the CPU implements the SPE extension, we need to return the
+ full 64-bit register. */
+ gprv = env->gpr[gprn].u64;
}
#endif
@@ -819,9 +821,9 @@
{
int i;
if (newsp)
- env->gpr[1] = newsp;
+ GPR(env, 1) = newsp;
for (i = 7; i < 32; i++)
- env->gpr[i] = 0;
+ GPR(env, i) = 0;
}
#endif
diff -r 5ed4e3fd0fe7 -r 8a7ea9ce5335 target-ppc/exec.h
--- a/target-ppc/exec.h Tue Oct 14 15:23:35 2008 -0400
+++ b/target-ppc/exec.h Wed Oct 15 08:45:29 2008 -0400
@@ -34,9 +34,24 @@
register struct CPUPPCState *env asm(AREG0);
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* no registers can be used */
-#define T0 (env->t0)
-#define T1 (env->t1)
-#define T2 (env->t2)
+#if defined(TARGET_PPC64)
+#define T0 (env->t0.u64)
+#define T1 (env->t1.u64)
+#define T2 (env->t2.u64)
+#else
+#if defined(WORDS_BIGENDIAN)
+#define HI 0
+#define LO 1
+#else
+#define HI 1
+#define LO 0
+#endif
+#define T0 (env->t0.u32[LO])
+#define T1 (env->t1.u32[LO])
+#define T2 (env->t2.u32[LO])
+#undef HI
+#undef LO
+#endif
#define TDX "%016" PRIx64
#else
register target_ulong T0 asm(AREG1);
@@ -46,9 +61,9 @@
#endif
/* We may, sometime, need 64 bits registers on 32 bits targets */
#if !defined(TARGET_PPC64)
-#define T0_64 (env->t0_64)
-#define T1_64 (env->t1_64)
-#define T2_64 (env->t2_64)
+#define T0_64 (env->t0.u64)
+#define T1_64 (env->t1.u64)
+#define T2_64 (env->t2.u64)
#else
#define T0_64 T0
#define T1_64 T1
diff -r 5ed4e3fd0fe7 -r 8a7ea9ce5335 target-ppc/helper_regs.h
--- a/target-ppc/helper_regs.h Tue Oct 14 15:23:35 2008 -0400
+++ b/target-ppc/helper_regs.h Wed Oct 15 08:45:29 2008 -0400
@@ -44,17 +44,17 @@
{
target_ulong tmp;
- tmp = env->gpr[0];
- env->gpr[0] = env->tgpr[0];
+ tmp = GPR(env, 0);
+ GPR(env, 0) = env->tgpr[0];
env->tgpr[0] = tmp;
- tmp = env->gpr[1];
- env->gpr[1] = env->tgpr[1];
+ tmp = GPR(env, 1);
+ GPR(env, 1) = env->tgpr[1];
env->tgpr[1] = tmp;
- tmp = env->gpr[2];
- env->gpr[2] = env->tgpr[2];
+ tmp = GPR(env, 2);
+ GPR(env, 2) = env->tgpr[2];
env->tgpr[2] = tmp;
- tmp = env->gpr[3];
- env->gpr[3] = env->tgpr[3];
+ tmp = GPR(env, 3);
+ GPR(env, 3) = env->tgpr[3];
env->tgpr[3] = tmp;
}
diff -r 5ed4e3fd0fe7 -r 8a7ea9ce5335 target-ppc/op_helper_mem.h
--- a/target-ppc/op_helper_mem.h Tue Oct 14 15:23:35 2008 -0400
+++ b/target-ppc/op_helper_mem.h Wed Oct 15 08:45:29 2008 -0400
@@ -24,7 +24,7 @@
void glue(do_lmw, MEMSUFFIX) (int dst)
{
for (; dst < 32; dst++, T0 += 4) {
- env->gpr[dst] = glue(ldu32, MEMSUFFIX)((uint32_t)T0);
+ GPR(env, dst) = glue(ldu32, MEMSUFFIX)((uint32_t)T0);
}
}
@@ -32,7 +32,7 @@
void glue(do_lmw_64, MEMSUFFIX) (int dst)
{
for (; dst < 32; dst++, T0 += 4) {
- env->gpr[dst] = glue(ldu32, MEMSUFFIX)((uint64_t)T0);
+ GPR(env, dst) = glue(ldu32, MEMSUFFIX)((uint64_t)T0);
}
}
#endif
@@ -40,7 +40,7 @@
void glue(do_stmw, MEMSUFFIX) (int src)
{
for (; src < 32; src++, T0 += 4) {
- glue(st32, MEMSUFFIX)((uint32_t)T0, env->gpr[src]);
+ glue(st32, MEMSUFFIX)((uint32_t)T0, GPR(env, src));
}
}
@@ -48,7 +48,7 @@
void glue(do_stmw_64, MEMSUFFIX) (int src)
{
for (; src < 32; src++, T0 += 4) {
- glue(st32, MEMSUFFIX)((uint64_t)T0, env->gpr[src]);
+ glue(st32, MEMSUFFIX)((uint64_t)T0, GPR(env, src));
}
}
#endif
@@ -56,7 +56,7 @@
void glue(do_lmw_le, MEMSUFFIX) (int dst)
{
for (; dst < 32; dst++, T0 += 4) {
- env->gpr[dst] = glue(ldu32r, MEMSUFFIX)((uint32_t)T0);
+ GPR(env, dst) = glue(ldu32r, MEMSUFFIX)((uint32_t)T0);
}
}
@@ -64,7 +64,7 @@
void glue(do_lmw_le_64, MEMSUFFIX) (int dst)
{
for (; dst < 32; dst++, T0 += 4) {
- env->gpr[dst] = glue(ldu32r, MEMSUFFIX)((uint64_t)T0);
+ GPR(env, dst) = glue(ldu32r, MEMSUFFIX)((uint64_t)T0);
}
}
#endif
@@ -72,7 +72,7 @@
void glue(do_stmw_le, MEMSUFFIX) (int src)
{
for (; src < 32; src++, T0 += 4) {
- glue(st32r, MEMSUFFIX)((uint32_t)T0, env->gpr[src]);
+ glue(st32r, MEMSUFFIX)((uint32_t)T0, GPR(env, src));
}
}
@@ -80,7 +80,7 @@
void glue(do_stmw_le_64, MEMSUFFIX) (int src)
{
for (; src < 32; src++, T0 += 4) {
- glue(st32r, MEMSUFFIX)((uint64_t)T0, env->gpr[src]);
+ glue(st32r, MEMSUFFIX)((uint64_t)T0, GPR(env, src));
}
}
#endif
@@ -91,7 +91,7 @@
int sh;
for (; T1 > 3; T1 -= 4, T0 += 4) {
- env->gpr[dst++] = glue(ldu32, MEMSUFFIX)((uint32_t)T0);
+ GPR(env, dst++) = glue(ldu32, MEMSUFFIX)((uint32_t)T0);
if (unlikely(dst == 32))
dst = 0;
}
@@ -100,7 +100,7 @@
for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
tmp |= glue(ldu8, MEMSUFFIX)((uint32_t)T0) << sh;
}
- env->gpr[dst] = tmp;
+ GPR(env, dst) = tmp;
}
}
@@ -111,7 +111,7 @@
int sh;
for (; T1 > 3; T1 -= 4, T0 += 4) {
- env->gpr[dst++] = glue(ldu32, MEMSUFFIX)((uint64_t)T0);
+ GPR(env, dst++) = glue(ldu32, MEMSUFFIX)((uint64_t)T0);
if (unlikely(dst == 32))
dst = 0;
}
@@ -120,7 +120,7 @@
for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
tmp |= glue(ldu8, MEMSUFFIX)((uint64_t)T0) << sh;
}
- env->gpr[dst] = tmp;
+ GPR(env, dst) = tmp;
}
}
#endif
@@ -130,13 +130,13 @@
int sh;
for (; T1 > 3; T1 -= 4, T0 += 4) {
- glue(st32, MEMSUFFIX)((uint32_t)T0, env->gpr[src++]);
+ glue(st32, MEMSUFFIX)((uint32_t)T0, GPR(env, src++));
if (unlikely(src == 32))
src = 0;
}
if (unlikely(T1 != 0)) {
for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
- glue(st8, MEMSUFFIX)((uint32_t)T0, (env->gpr[src] >> sh) & 0xFF);
+ glue(st8, MEMSUFFIX)((uint32_t)T0, (GPR(env, src) >> sh) & 0xFF);
}
}
@@ -146,13 +146,13 @@
int sh;
for (; T1 > 3; T1 -= 4, T0 += 4) {
- glue(st32, MEMSUFFIX)((uint64_t)T0, env->gpr[src++]);
+ glue(st32, MEMSUFFIX)((uint64_t)T0, GPR(env, src++));
if (unlikely(src == 32))
src = 0;
}
if (unlikely(T1 != 0)) {
for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
- glue(st8, MEMSUFFIX)((uint64_t)T0, (env->gpr[src] >> sh) & 0xFF);
+ glue(st8, MEMSUFFIX)((uint64_t)T0, (GPR(env, src) >> sh) & 0xFF);
}
}
#endif
@@ -294,7 +294,7 @@
c = glue(ldu8, MEMSUFFIX)((uint32_t)T0++);
/* ra (if not 0) and rb are never modified */
if (likely(reg != rb && (ra == 0 || reg != ra))) {
- env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
+ GPR(env, reg) = (GPR(env, reg) & ~(0xFF << d)) | (c << d);
}
if (unlikely(c == T2))
break;
diff -r 5ed4e3fd0fe7 -r 8a7ea9ce5335 target-ppc/translate.c
--- a/target-ppc/translate.c Tue Oct 14 15:23:35 2008 -0400
+++ b/target-ppc/translate.c Wed Oct 15 08:45:29 2008 -0400
@@ -46,17 +45,20 @@
/* global register indexes */
static TCGv cpu_env;
-static char cpu_reg_names[10*3 + 22*4 /* GPR */
-#if !defined(TARGET_PPC64)
- + 10*4 + 22*5 /* SPE GPRh */
-#endif
- + 10*4 + 22*5 /* FPR */
- + 2*(10*6 + 22*7) /* AVRh, AVRl */
- + 8*5 /* CRF */];
+/* 10 single-digit names + 22 double-digit names */
+#define REG_NAME_LEN(prefix) ((sizeof(prefix)+1)*32 + 22)
+static char cpu_reg_names[REG_NAME_LEN("r") /* GPR */
+ + REG_NAME_LEN("rH") /* SPE GPRh */
+ + REG_NAME_LEN("rL") /* SPE GPRl */
+ + REG_NAME_LEN("r64") /* 64-bit GPRs */
+ + REG_NAME_LEN("fp") /* FPR */
+ + REG_NAME_LEN("avrH") /* AVRh */
+ + REG_NAME_LEN("avrL") /* AVRl */
+ + 8*5 /* CRF */];
static TCGv cpu_gpr[32];
-#if !defined(TARGET_PPC64)
static TCGv cpu_gprh[32];
-#endif
+static TCGv cpu_gprl[32];
+static TCGv cpu_gpr64[32];
static TCGv cpu_fpr[32];
static TCGv cpu_avrh[32], cpu_avrl[32];
static TCGv cpu_crf[8];
@@ -86,7 +88,15 @@
return;
cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
+#if defined(WORDS_BIGENDIAN)
+#define HI 0
+#define LO 1
+#else
+#define HI 1
+#define LO 0
+#endif
#if TARGET_LONG_BITS > HOST_LONG_BITS
+#if defined(TARGET_PPC64)
cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, t0), "T0");
cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
@@ -94,19 +104,27 @@
cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, t2), "T2");
#else
+ cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, t0.u32[LO]),
"T0");
+ cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, t1.u32[LO]),
"T1");
+ cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, t2.u32[LO]),
"T2");
+#endif
+#else
cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
#endif
#if !defined(TARGET_PPC64)
cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
- TCG_AREG0, offsetof(CPUState, t0_64),
+ TCG_AREG0, offsetof(CPUState, t0.u64),
"T0_64");
cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
- TCG_AREG0, offsetof(CPUState, t1_64),
+ TCG_AREG0, offsetof(CPUState, t1.u64),
"T1_64");
cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
- TCG_AREG0, offsetof(CPUState, t2_64),
+ TCG_AREG0, offsetof(CPUState, t2.u64),
"T2_64");
#endif
@@ -118,17 +136,17 @@
offsetof(CPUState, ft2), "FT2");
cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
- offsetof(CPUState, avr0.u64[0]), "AVR0H");
+ offsetof(CPUState, avr0.u64[HI]),
"AVR0H");
cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
- offsetof(CPUState, avr0.u64[1]), "AVR0L");
+ offsetof(CPUState, avr0.u64[LO]),
"AVR0L");
cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
- offsetof(CPUState, avr1.u64[0]), "AVR1H");
+ offsetof(CPUState, avr1.u64[HI]),
"AVR1H");
cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
- offsetof(CPUState, avr1.u64[1]), "AVR1L");
+ offsetof(CPUState, avr1.u64[LO]),
"AVR1L");
cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
- offsetof(CPUState, avr2.u64[0]), "AVR2H");
+ offsetof(CPUState, avr2.u64[HI]),
"AVR2H");
cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
- offsetof(CPUState, avr2.u64[1]), "AVR2L");
+ offsetof(CPUState, avr2.u64[LO]),
"AVR2L");
p = cpu_reg_names;
@@ -141,16 +159,26 @@
for (i = 0; i < 32; i++) {
sprintf(p, "r%d", i);
+#if defined(TARGET_PPC64)
cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
- offsetof(CPUState, gpr[i]), p);
+ offsetof(CPUState, gpr[i].u64), p);
+#else
+ cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ offsetof(CPUState, gpr[i].u32[LO]), p);
+#endif
p += (i < 10) ? 3 : 4;
-#if !defined(TARGET_PPC64)
sprintf(p, "r%dH", i);
cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
- offsetof(CPUState, gprh[i]), p);
+ offsetof(CPUState, gpr[i].u32[HI]),
p);
p += (i < 10) ? 4 : 5;
-#endif
-
+ sprintf(p, "r%dL", i);
+ cpu_gprl[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
+ offsetof(CPUState, gpr[i].u32[LO]),
p);
+ p += (i < 10) ? 4 : 5;
+ sprintf(p, "r%d64", i);
+ cpu_gpr64[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
+ offsetof(CPUState, gpr[i].u64), p);
+ p += (i < 10) ? 5 : 6;
sprintf(p, "fp%d", i);
cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
offsetof(CPUState, fpr[i]), p);
@@ -158,13 +186,15 @@
sprintf(p, "avr%dH", i);
cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
- offsetof(CPUState, avr[i].u64[0]), p);
+ offsetof(CPUState, avr[i].u64[HI]),
p);
p += (i < 10) ? 6 : 7;
sprintf(p, "avr%dL", i);
cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
- offsetof(CPUState, avr[i].u64[1]), p);
+ offsetof(CPUState, avr[i].u64[LO]),
p);
p += (i < 10) ? 6 : 7;
+#undef HI
+#undef LO
}
cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
diff -r 8a7ea9ce5335 -r 6585f5f2be1b hw/ppc405_boards.c
--- a/hw/ppc405_boards.c Wed Oct 15 08:45:29 2008 -0400
+++ b/hw/ppc405_boards.c Wed Oct 15 09:27:07 2008 -0400
@@ -297,7 +297,7 @@
bd.bi_pci_busfreq = 33333333;
bd.bi_opbfreq = 33333333;
bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
- env->gpr[3] = bdloc;
+ GPR(env, 3) = bdloc;
kernel_base = KERNEL_LOAD_ADDR;
/* now we can load the kernel */
kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
@@ -326,18 +326,18 @@
initrd_base = 0;
initrd_size = 0;
}
- env->gpr[4] = initrd_base;
- env->gpr[5] = initrd_size;
+ GPR(env, 4) = initrd_base;
+ GPR(env, 5) = initrd_size;
ppc_boot_device = 'm';
if (kernel_cmdline != NULL) {
len = strlen(kernel_cmdline);
bdloc -= ((len + 255) & ~255);
memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);
- env->gpr[6] = bdloc;
- env->gpr[7] = bdloc + len;
+ GPR(env, 6) = bdloc;
+ GPR(env, 7) = bdloc + len;
} else {
- env->gpr[6] = 0;
- env->gpr[7] = 0;
+ GPR(env, 6) = 0;
+ GPR(env, 7) = 0;
}
env->nip = KERNEL_LOAD_ADDR;
} else {
diff -r 8a7ea9ce5335 -r 6585f5f2be1b hw/ppc_oldworld.c
--- a/hw/ppc_oldworld.c Wed Oct 15 08:45:29 2008 -0400
+++ b/hw/ppc_oldworld.c Wed Oct 15 09:27:07 2008 -0400
@@ -47,49 +47,49 @@
/* same handler as PearPC, coming from the original MOL video
driver. */
- switch(env->gpr[5]) {
+ switch(GPR(env, 5)) {
case 4:
break;
case 28: /* set_vmode */
- if (env->gpr[6] != 1 || env->gpr[7] != 0)
- env->gpr[3] = 1;
+ if (GPR(env, 6) != 1 || GPR(env, 7) != 0)
+ GPR(env, 3) = 1;
else
- env->gpr[3] = 0;
+ GPR(env, 3) = 0;
break;
case 29: /* get_vmode_info */
- if (env->gpr[6] != 0) {
- if (env->gpr[6] != 1 || env->gpr[7] != 0) {
- env->gpr[3] = 1;
+ if (GPR(env, 6) != 0) {
+ if (GPR(env, 6) != 1 || GPR(env, 7) != 0) {
+ GPR(env, 3) = 1;
break;
}
}
- env->gpr[3] = 0;
- env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
- env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
- env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
- env->gpr[7] = 85 << 16; /* refresh rate */
- env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
+ GPR(env, 3) = 0;
+ GPR(env, 4) = (1 << 16) | 1; /* num_vmodes, cur_vmode */
+ GPR(env, 5) = (1 << 16) | 0; /* num_depths, cur_depth_mode */
+ GPR(env, 6) = (graphic_width << 16) | graphic_height; /* w, h */
+ GPR(env, 7) = 85 << 16; /* refresh rate */
+ GPR(env, 8) = (graphic_depth + 7) & ~7; /* depth (round to byte) */
linesize = ((graphic_depth + 7) >> 3) * graphic_width;
linesize = (linesize + 3) & ~3;
- env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
+ GPR(env, 9) = (linesize << 16) | 0; /* row_bytes, offset */
break;
case 31: /* set_video power */
- env->gpr[3] = 0;
+ GPR(env, 3) = 0;
break;
case 39: /* video_ctrl */
- if (env->gpr[6] == 0 || env->gpr[6] == 1)
- vga_vbl_enabled = env->gpr[6];
- env->gpr[3] = 0;
+ if (GPR(env, 6) == 0 || GPR(env, 6) == 1)
+ vga_vbl_enabled = GPR(env, 6);
+ GPR(env, 3) = 0;
break;
case 47:
break;
case 59: /* set_color */
/* R6 = index, R7 = RGB */
- env->gpr[3] = 0;
+ GPR(env, 3) = 0;
break;
case 64: /* get color */
/* R6 = index */
- env->gpr[3] = 0;
+ GPR(env, 3) = 0;
break;
case 116: /* set hwcursor */
/* R6 = x, R7 = y, R8 = visible, R9 = data */
diff -r 6585f5f2be1b -r f465712154ba darwin-user/main.c
--- a/darwin-user/main.c Wed Oct 15 09:27:07 2008 -0400
+++ b/darwin-user/main.c Wed Oct 15 09:57:12 2008 -0400
@@ -491,21 +491,21 @@
case POWERPC_EXCP_SYSCALL_USER:
/* system call in user-mode emulation */
/* system call */
- if(((int)env->gpr[0]) <= SYS_MAXSYSCALL && ((int)env->gpr[0])>0)
- ret = do_unix_syscall(env, env->gpr[0]/*, env->gpr[3],
env->gpr[4],
- env->gpr[5], env->gpr[6], env->gpr[7],
- env->gpr[8], env->gpr[9],
env->gpr[10]*/);
- else if(((int)env->gpr[0])<0)
- ret = do_mach_syscall(env, env->gpr[0], env->gpr[3],
env->gpr[4],
- env->gpr[5], env->gpr[6], env->gpr[7],
- env->gpr[8], env->gpr[9], env->gpr[10]);
+ if(((int)GPR(env, 0)) <= SYS_MAXSYSCALL && ((int)GPR(env, 0))>0)
+ ret = do_unix_syscall(env, GPR(env, 0)/*, GPR(env, 3),
GPR(env, 4),
+ GPR(env, 5), GPR(env, 6), GPR(env, 7),
+ GPR(env, 8), GPR(env, 9), GPR(env,
10)*/);
+ else if(((int)GPR(env, 0))<0)
+ ret = do_mach_syscall(env, GPR(env, 0), GPR(env, 3), GPR(env,
4),
+ GPR(env, 5), GPR(env, 6), GPR(env, 7),
+ GPR(env, 8), GPR(env, 9), GPR(env, 10));
else
- ret = do_thread_syscall(env, env->gpr[0], env->gpr[3],
env->gpr[4],
- env->gpr[5], env->gpr[6], env->gpr[7],
- env->gpr[8], env->gpr[9],
env->gpr[10]);
+ ret = do_thread_syscall(env, GPR(env, 0), GPR(env, 3),
GPR(env, 4),
+ GPR(env, 5), GPR(env, 6), GPR(env, 7),
+ GPR(env, 8), GPR(env, 9), GPR(env,
10));
/* Unix syscall error signaling */
- if(((int)env->gpr[0]) <= SYS_MAXSYSCALL && ((int)env->gpr[0])>0)
+ if(((int)GPR(env, 0)) <= SYS_MAXSYSCALL && ((int)GPR(env, 0))>0)
{
if( (int)ret < 0 )
env->nip += 0;
@@ -514,7 +514,7 @@
}
/* Return value */
- env->gpr[3] = ret;
+ GPR(env, 3) = ret;
break;
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
@@ -1027,7 +1027,7 @@
#endif
env->nip = regs->nip;
for(i = 0; i < 32; i++) {
- env->gpr[i] = regs->gpr[i];
+ GPR(env, i) = regs->gpr[i];
}
}
#else
diff -r 6585f5f2be1b -r f465712154ba darwin-user/qemu.h
--- a/darwin-user/qemu.h Wed Oct 15 09:27:07 2008 -0400
+++ b/darwin-user/qemu.h Wed Oct 15 09:57:12 2008 -0400
@@ -162,7 +162,7 @@
static inline uint32_t get_int_arg(int *i, CPUPPCState *cpu_env)
{
/* XXX: won't work when args goes on stack after gpr10 */
- uint32_t args = (uint32_t)(cpu_env->gpr[3+(*i & 0xff)/4]);
+ uint32_t args = (uint32_t)(GPR(cpu_env, 3+(*i & 0xff)/4));
*i+=4;
return tswap32(args);
}
diff -r 6585f5f2be1b -r f465712154ba darwin-user/syscall.c
--- a/darwin-user/syscall.c Wed Oct 15 09:27:07 2008 -0400
+++ b/darwin-user/syscall.c Wed Oct 15 09:57:12 2008 -0400
@@ -963,11 +963,11 @@
#elif TARGET_PPC
{
int i;
- uint32_t **regs = ((CPUPPCState*)cpu_env)->gpr;
+ CPUPPCState *env = (CPUPPCState*)cpu_env;
for(i = 3; i < 11; i++)
- *regs[i] = *regs[i+1];
+ GPR(env, i) = GPR(env, i+1);
/* XXX: not necessary */
- *regs[0] = new_num;
+ GPR(env, 0) = new_num;
}
#endif
ret = do_unix_syscall(cpu_env, new_num);
@@ -979,11 +979,11 @@
{
int i;
/* XXX: not really needed those regs are volatile accross calls */
- uint32_t **regs = ((CPUPPCState*)cpu_env)->gpr;
+ CPUPPCState *env = (CPUPPCState*)cpu_env;
for(i = 11; i > 3; i--)
- *regs[i] = *regs[i-1];
- regs[3] = new_num;
- *regs[0] = num;
+ GPR(env, i) = GPR(env, i-1);
+ GPR(env, 3) = new_num;
+ GPR(env, 0) = num;
}
#endif
return ret;
@@ -1225,7 +1225,7 @@
((CPUX86State *)cpu_env)->regs[R_EDX] = (uint32_t)((r >> 32) & 0xffffffff)
;
#elif defined TARGET_PPC
ret = r & 0xffffffff; /* will be set to r3 after do_unix_syscall exit */
- ((CPUPPCState *)cpu_env)->gpr[4] = (uint32_t)((r >> 32) & 0xffffffff) ;
+ GPR(((CPUPPCState *)cpu_env), 4) = (uint32_t)((r >> 32) & 0xffffffff) ;
#else
qerror("64 bit ret value on your arch?");
#endif
diff -r 6585f5f2be1b -r f465712154ba target-ppc/helper.c
--- a/target-ppc/helper.c Wed Oct 15 09:27:07 2008 -0400
+++ b/target-ppc/helper.c Wed Oct 15 09:57:12 2008 -0400
@@ -2349,7 +2349,7 @@
/* NOTE: this is a temporary hack to support graphics OSI
calls from the MOL driver */
/* XXX: To be removed */
- if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
+ if (GPR(env, 3) == 0x113724fa && GPR(env, 4) == 0x77810f9b &&
env->osi_call) {
if (env->osi_call(env) != 0) {
env->exception_index = POWERPC_EXCP_NONE;
- [Qemu-devel] [PATCH][ppc] reorganize register set for SPE + TCG,
Nathan Froyd <=