[Qemu-devel] [PATCH] SH: Add prefi, icbi, synco

[Vladimir Prus]

This patch makes qemu recognize (and ignore), three instructions from SH4A.
First if prefetch (prefi). QEMU does not model cache, and the instruction is
documented to never cause TLB miss. Second is icbi, which invalidates cache
block, and again, no cache is simulated. Last is synco, which is memory barrier,
but qemu does not reorder memory operations anyway, I think.

- Volodya

        * target-sh4/translate.c (_decode_opc): Handle
        prefi, icbi, and synco.
---
 target-sh4/translate.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 0eeb294..bf86329 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1552,6 +1552,12 @@ void _decode_opc(DisasContext * ctx)
        return;
     case 0x0083:               /* pref @Rn */
        return;
+    case 0x00d3:               /* prefi @Rn */
+       return;
+    case 0x00e3:               /* icbi @Rn */
+       return;
+    case 0x00ab:               /* synco */
+       return;
     case 0x4024:               /* rotcl Rn */
        {
            TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
-- 
1.5.3.5